本論文提出各式參考電壓源應用於光獵能系統，以超低功耗 CMOS 偏壓電
路與高精度帶隙參考電壓電路來為整個光獵能系統中的各個電路提供偏壓，如：
運算放大器、溫度感測器、類比至數位轉換器等電路提供穩定的偏壓。因超低
功耗 CMOS 參考電壓源往往需要運算放大器來提升其電源電壓抑制比，非但需
要消耗更多的面積與功耗，運算放大器的偏壓也會是一大問題，因此無法針對
不同電路環境下做最佳化。為解決需要額外加入運算放大器提升電源電壓抑制
比的問題，本論文使用一新型超低功耗參考電壓電路架構，得以在無需加入運
算放大器的情況下有效提升電源電壓抑制比，並利用基底偏壓回授來對高溫電
壓進行補償，讓電壓參考電路有寬裕的溫度工作與電源電壓變動範圍。
帶隙參考電壓電路因運算放大器差動輸入對的偏移電壓對總輸出電壓有嚴
重的影響，傳統高精度帶隙參考電壓電路需要加入額外的補償機制來對降低其
輸出電壓的偏移量，此方法需要引入額外的控制訊號源且具複雜的邏輯控制，
導致成本與設計難度上升。本論文亦提出一無需補償機制之 BJT 與 CMOS 混合
使用的帶隙參考電壓電路架構，無須額外使用偏移消除的複雜電路與控制訊號
即可達成高精度輸出電壓，並將第一個作品的低功耗參考電壓源進行改版後供
應穩定電壓給運算放大器，從而實現低功耗的目標。
本論文下線晶片使用 TSMC 0.18μm CMOS 標準製程實現，低功耗電壓源整
體晶片佈局面積含 I/O pads 為 0.437mm2，後模擬結果為輸出電壓為 259mV，
TC=10.28ppm、電源電壓抑制比為-80dB，功率消耗為 6.17nW。高精度帶隙參
考電壓源整體晶片佈局面積含 I/O pads 為 0.938mm2，後模擬結果為輸出電壓為
1.271V，TC=6.94ppm 電源電壓抑制比為-81dB，功率消耗為 17.6uW，輸出電壓
偏移量為 0.15 %。

This thesis proposes various reference voltage sources for use in solar energy
harvesting systems. Ultra-low power CMOS voltage reference and high-precision
bandgap reference voltage circuits are used to provide bias for various blocks in the
entire solar energy harvesting system, such as operational amplifiers, temperature
sensors, and analog-to-digital converters, to provide stable bias voltage. Ultra-low
power CMOS reference voltage sources often require operational amplifiers to enhance
their power supply rejection ratio. It not only consumes more area and power, but also
becomes a major design issue to make it impossible for different circuit optimizations.
To solve the problem of the need of additional operational amplifiers to enhance
power supply rejection ratio, this thesis proposes a new type of ultra-low power
reference voltage circuit architecture that can effectively improve power supply
rejection ratio without operational amplifiers. Furthermore, the substrate bias feedback
is used to compensate for high-temperature voltage allowing the voltage reference
circuit to have a wide temperature operating range and power supply voltage variation.
Traditional high-precision bandgap reference voltage circuits require additional
compensation mechanisms to reduce the output voltage offset caused by the input offset
voltage of the operational amplifier. It requires additional control signal sources and
has complex logic control which increases cost and design difficulty. This thesis also
proposes a bandgap reference voltage circuit architecture that uses a combination of
BJT and CMOS without the need of compensation mechanism. High-precision output
voltage can be achieved without using complex circuitry and control signals to
eliminate input offset. The low-power reference voltage source of the first product is
revised to provide stable voltage to the operational amplifier for low power
consumption.
The final chips of this thesis are implemented in a TSMC 0.18μm CMOS standard
process. The overall chip layout area of the low-power voltage source, including I/O
pads, is 0.438mm2
. The post-simulation simulation results show that the output voltage
is 259mV, the temperature coefficient is 10.28ppm, the power supply rejection ratio is
-80dB, and the power consumption is 6.17nW. The overall chip layout area of the highprecision bandgap reference voltage source, including I/O pads, is 0.938mm2
. The postsimulation results show the output voltage is 1.271V, the temperature coefficient is
6.94ppm, the power supply rejection ratio is -81dB, the power consumption is 17.6uW,
and the output voltage offset is 0.15%.

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