在本論文中，我們設計與實現一個與ARM922T架構相容的系統協同處理器(System Coprocessor)智財(Intellectual Property, IP)，透過此協同處理器將Proto-ARM9M微處理器、16 K位元組的快取記憶體(Cache Memory)、記憶體管理單元(Memory Management Unit, MMU)與AMBA匯流排介面(AMBA Bus Interface)整合成微處理器智財－Proto-ARM922。系統協同處理器的資料路徑(Data Path)為5級管線架構，由指令解碼器(Instruction Decoder)、暫存器陣列(Register File)與交握模組(Handshake Unit)所組成，可透過專用指令控制記憶體管理單元、快取記憶體、以及系統協同處理器與Proto-ARM9M之間的資料傳輸。
目前系統協同處理器已整合了Proto-ARM9M、16 K位元組的快取記憶體與AMBA匯流排介面於Xilinx的Spartan-3 XC3S1500-4FG676 FPGA以及TSMC 0.18 μm元件庫上實現。FPGA設計驗證部分，共使用了12901個LUTs，最高操作頻率可達14 MHz，並於實驗板上搭配自行開發的測試環境以驗證所有測試程式及功能。元件庫方面，核心面積為2580.48 μm × 2586.06 μm，等效閘數(Gate Count)為382854閘，整體晶片面積為3250.92 μm × 3256.34 μm，在SS模式下操作頻率為50 MHz。

In this thesis, a system coprocessor IP (Intellectual Property) compatible with ARM922T architecture, denoted as a Proto-ARM922 system coprocessor, is proposed. Through this coprocessor, the Proto-ARM9M microprocessor, a 16-KB cache memory, an MMU, and an AMBA bus interface are combined with the Proto-ARM922 processor into an integrated system. The datapath of the system coprocessor is a five-stage pipeline consisting of instruction decoder, register file, and handshake unit, and is used to control MMU, cache memory, and transferred data from/to Proto-ARM9M microprocessor through some dedicated instructions.
The resulting system has been implemented and verified with Xilinx Spartan-3 XC3S1500-4FG676 FPGA and TSMC 0.18 μm cell library. In the FPGA part, it takes 12901 LUTs and operates at the maximum working frequency of 14 MHz. In the cell-based part, the core occupies 2580.48 μm × 2586.06 μm, which is approximately equivalent to 382854 gates, and the whole chip occupies 3250.92 μm × 3256.34 μm, and in the SS (Slow NMOS Slow PMOS model) simulation condition it operates at the maximum working frequency of 50 MHz.

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