本論文是有關時序中值濾波背景相減演算處理系統之軟/硬整合設計與驗證，相關研究工作包含下列四大部分：
第一部份為時序中值濾波(Temporal Median Filter)背景相減(Background Subtraction)演算法之相關軟體設計，並以影像輸出結果展示其應用之優越性。
第二部份為設計與實現時序中值濾波背景相減演算處理器，其中包含了影像資料提取副處理器、中值搜尋副處理器及背景相減副處理器；最後，將以上設計之硬體整合於單晶片可程式化系統中，並以Altera FPGA開發板實現之。
第三部份是有關演算處理系統之設計與實現，其包括用以儲存多張完整影像之同步動態記憶體、上述之演算處理器、NIOS II CPU及相關軟韌體，並以NIOS II IDE來驗證其功能。
第四部份是分析及評估演算處理系統之整體軟韌體及硬體效能。
整體而言，本論文係以研究時序中值濾波背景相減演算法與設計其演算處理系統為目標，並將其實現於Altera FPGA開發板上。透過各種不同的輸入影像之實驗測試，證實本論文所發展之演算處理系統，有極佳的效能，其設計方法亦可改善演算處理系統設計與驗證流程的效率。

This thesis is relevant to the hardware/software co-design and implementation of a temporal-median-filter-based algorithmic processing system for background subtraction. The research work consists of the following four parts.

The first part is related to the software design of the temporal-median-filter-based background subtraction algorithm. Meanwhile, through using the image-based output results, this algorithm has demonstrated its superiority in various applications.

The second part is to design and implement a temporal-median-filter-based algorithmic processor for background subtraction. This algorithmic processor comprises three subprocessors which are for image information access, median finding, and background subtraction. Finally, all these parts mentioned above are integrated together and implemented on an Altera FPGA development board.

The third part is related to the design and implementation of an algorithmic processing system which comprises SDRAM (for storing multiple complete images), the algorithmic processor described above, NIOS II CPU, and the related firmware. Meanwhile, the functionality of this system is verified through using NIOS II IDE.

The fourth part is to analyze and evaluate the software, firmware, and hardware performance of the whole algorithmic processing system.

On the whole, the goals of this thesis are to do research on a temporal-median-filter-based background subtraction algorithm and design an algorithmic processing system (on an Altera FPGA development board) for it. After being verified with various kinds of digital images, the algorithmic processing system developed in this thesis has shown fabulous computing performance and the related hardware/software co-design method can also be used to improve the efficiency of the design and verification process for other algorithmic processing systems.

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