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研究生： 馮鈞雅
Jun-Ya Feng
論文名稱： 基於RFC2544 之多核心高速網路效能評估平台開發
Development of Network Performance Evaluation Platform via Advanced Multicore Architecture Based on RFC2544
指導教授： 阮聖彰
Shanq-Jang Ruan
口試委員: 呂政修
Jenq-Shiou Leu
吳晉賢
Chin-Hsien Wu
林淵翔
Yuan-Hsiang Lin
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2015
畢業學年度： 103
語文別： 英文
論文頁數： 50
中文關鍵詞： 網路效能測試平台 、多核心架構 、RFC2544
外文關鍵詞： RFC2544, Network Performance Platform, OSI layer 4, Multicore Architecture
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    • 由於雲端應用帶來大量的網路使用需求，高速網路設備與智慧化網路設備將是網通產業發展的重要市場，透過RFC 2544 制定的標準，各家供應商可以在統一的標準內評估各自設備的效能。本論文針對高速網路設備設計一個測試的平台與環境，並使用RFC1242 與RFC 2544 為測試流程的標準，此平台主要包含一個設定與控制系統、一個網路流量產生器與結果分析器以及針對各測試項目所設計的測試環境與流程，設定與控制系統可遠端透過網路進行操作，網路流量產生器與結果分析器則透過先進多核心系統進行實作，測試項目除了傳統的Layer 2 與Layer 3 網路封包處理外，亦包含Layer 4 的設計。

    Nowadays, the development of networking service has grown, requirement for high performance network equipment have increased significantly. In order to have high quality of services and better network security, in addition to support layer 2 and layer 3, the development of equipment began to support OSI layer 4. Hence, we require accurate estimations of network performance metrics to analyze performance of connected network device. Protocol RFC1242 and RFC2544 are international standard to evaluate network equipment. These protocol define four important metrics to analyze connected network devices, including throughput, latency, frame loss rate and back-to-back performance. In this thesis, we design a network performance evaluation platform by using multicore architectures based on RFC2544. Unlike other market products, our design can support on layer 4 throughput performance test.

    Recommendation Form Committee Form Chinese Abstract English Abstract Acknowledgements Table of Contents List of Tables List of Figures 1 Introduction 1.1 Motivation 1.2 Introduction to Network Standard 1.3 Organization of This Thesis 2 Background 2.1 RFC2544 2.1.1 Throughput 2.1.2 Latency 2.1.3 Frame Loss 2.1.4 Back-to-Back 2.2 The Open System Interconnection Reference Model 2.2.1 Physical Layer 2.2.2 Data Link Layer 2.2.3 Network Layer 2.2.4 Transport Layer 2.2.5 Session Layer 2.2.6 Presentation Layer 2.2.7 Application Layer 2.3 Tilera Platform Architecture 3 Proposed Method 3.1 Linux Server 3.2 Our Proposed Method in The Tilera Platform 3.2.1 Traffic Generator 3.2.2 Result Analyzer 3.3 Four Testing Items by using Our Proposed Method 3.3.1 Throughput 3.3.2 Latency 3.3.3 Frame Loss 3.3.4 Back-to-Back 3.4 Device Under Test Equipment 4 Experimental Results 4.1 Four Layers Experimental Results 4.2 Comparison with Other System 5 Conclusions References Copyright Form

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    [15] "TILE-Gx8036 product brief", http:// www.tilera.com/ files/ drim__TILEGx8036_PB033-03_WEB_7682.pdf
    [16] D. Wentzlaff, et al "On-chip interconnection architecture of the tile processor", IEEE Computer Society., 2007
    [17] "Tile processor user architecture manual", http://www.tilera.com/scm/docs/UG101-User-Architecture-Reference.pdf

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