提出利用雙倍暫存器，使得編譯器或程式設計師可以使用更多的暫存器提高程式的效率，更重要的是此指令格式不會增加額外的位元使指令長度增加。利用這方法我們可以將 ARM 微處理器中暫存器的數目增為原本的 2 倍，讓 32 位元的指令可以使用的暫存器從 16 個增加到 32 個，使得編譯器或程式設計師可以使用 32 個暫存器來存放變數或計算結果，提高程式的效率。

雖然藉由增加暫存器，提升程式效率是很普遍的方式，但如果不增加額外的位元在指令中處理所增加的暫存器數目，那勢必在程式中必須替換 ARM 處理器原有的功能，使暫存器增加。而在本篇論文中我們提出兩個方法，希望保留 ARM 原有的功能並且增加一倍的暫存器數目，進而使程式效率提升。

Proposed use of the double registers, the compiler or the programmer can use more registers to improve the efficiency of the program. It is important the instruction format does not add an extra bit instruction length increases. This method can be ARM micro processor registers the number increased to 2-fold, 32-bit instruction register that can be used from 16 to 32, making the compiler or the programmer 32 registers for storing variables or calculated results, improve the efficiency of the program.

By additional registers, improve program efficiency is very common, but if you do not increase the number of extra bits in the instruction register to handle the increased, it is bound to replace the ARM processor in the program must be original function, so that register increases. In this paper, we propose two methods, and want to preserve the original features of the ARM and doubling the register number, and thus make the program efficiency.

[1] ARM Limited. ARM9TDMITM Technical Reference Manual,2000.

[2] Todd Austin, David Blaauw, Scott Mahlke, Trevor Mudge,Chaitali Chakrabarti, and Wayne Wolf. Mobile supercomputers.
IEEE Computer, 37(5):81–83, May 2004.

[3] Todd Austin, Eric Larson, and Dan Ernst. SimpleScalar:
An infrastructure for computer system modeling.
IEEEComputer, 35(2):59–67, 2002.

[4] Huang-Jia Cheng and Yuan-Shin Hwang. Trading conditional execution for more registers on ARM.
In Proceedings of the 2010 EUC, pages 53–59, 2010.

[5] Edil S. T. Fernandes, Anna Dolejsi Santos, and Claudio L. de Amorim. Conditional execution:
An approach for eliminatingthe basic block barriers. Microprocessing and Microprogrammin,40:689–692, 1994.

[6] Jason Fritts and Bill Mangione-Smith. MediaBench II -technology, status, and cooperation. In Proceedings of the Workshop on Media and Stream Processors, 2002.

[7] GCC. The GNU compiler collection. http://gcc.gnu.org/. 
[8] Wen-Mei Hwu. Technology outlook: Introduction to predicated execution. IEEE Computer, 31(1):49–50, January 1998.

[9] Intel Corporation. IntelR StrongARM SA-1110 Microprocessor Developer’s Manual, October 2001.

[10] Tokuzo Kiyohara, Scott Mahlke, William Chen, Roger Bringmann, Richard Hank, Sadun Anik, and Wen-Mei Hwu.
Register connection: a new approach to adding registers into instruction set architectures. In Proceedings of the 20th annual international symposium on Computer architecture, pages 247–256, 1993.

[11] Arvind Krishnaswamy and Rajiv Gupta. Efficient use of invisible registers in thumb code. In Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’05), 2005.

[12] Chunho Lee, Miodrag Potkonjak, and William H. Mangionesmith.
MediaBench: A tool for evaluating and synthesizing multimedia and communications systems. In Proceedings of the 30th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’97), pages 330–335, 1997.

[13] Joseph C. H. Park and Mike Schlansker. On predicated execution. Technical Report HPL-91-58, HP Labs, 1991.
 
[14] David Seal, editor. ARM Architecture Reference Manual.
Addison-Wesley Professional, 2nd edition, 2001.

[15] Simon Segars. Low power design techniques for microprocessors.
In 2001 IEEE International Solid-State Circuits Conference (ISSCC), 2001.

[16] Xiaotong Zhuang and Santosh Pande. Differential register allocation. In Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
(PLDI’05), pages 168–179, 2005.

[17] Xiaotong Zhuang, Tao Zhang, and Santosh Pande. Hardwaremanaged register allocation for embedded processors.
In Proceedings of the 2004 ACM SIGPLAN/SIGBED conference
on Languages, compilers, and tools for embedded systems,
pages 192–201, 2004.

[18] J.H. Lee, J. Park, S.M. Moon. Securing More Registers with Reduced Instruction Encoding Architectures. In Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA’07), pages 417-425, 2007