簡易檢索 / 詳目顯示

研究生: 傅從超
Cong-chao Fu
論文名稱: LC雙線性混波除四注入鎖定除頻器之熱載子效應與設計
Hot-Carrier Effect and Design of LC Divide-by-4 Injection-Locked Frequency Divider Using Two Linear Mixers
指導教授: 張勝良
Sheng-lyang Jang
口試委員: 徐敬文
Ching-wen Hsue
馮武雄
Wu-shiung Feng
黃進芳
Jhin-fang Huang
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2013
畢業學年度: 101
語文別: 英文
論文頁數: 103
中文關鍵詞: 熱載子應力效應振盪頻率可調範圍相位雜訊鎖定範圍可靠度寬頻線性混波注入鎖定除四除頻器串聯可調注入鎖定除二除頻器
外文關鍵詞: hot carrier stress, oscillating frequency, tuning range, phase noise, locking range, reliability, wide-band, linear mixer, divide-by-4 injection-locked frequency divider, series-tuned divide-by-2 injection-locked freque
相關次數: 點閱:368下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

首先,本論文提出一個新穎寬鎖定範圍除四注入鎖定除頻器,利用台灣積體電路公司(TSMC)之0.18 微米製程完成。這顆除四注入鎖定除頻器利用交叉耦合與並聯可調共振腔之壓控振盪器,加上由主被動元件混合組成的非線性混波器。當驅動偏壓為0.8伏特且注入訊號強度為0 dBm時,除四注入鎖定除頻器之操作範圍可接受注入訊號從10.5 GHz到12.7 GHz,除頻大小2.2 GHz除頻比例為18.96%。其鎖定範圍可接受注入訊號從10.6 GHz到12.2 GHz,除頻大小1.6 GHz除頻比例為14.035%。此除頻器之核心功耗為10.6毫瓦,所占面積為0.492×0.819毫米平方。
其次,我們探討在寬鎖定範圍除四注入鎖定除頻器上的交流熱載子效應,同樣是利用台灣積體電路公司(TSMC)之0.18 微米製程完成。直接經由金屬氧化半導體電晶體注入外部訊號耦合到共振腔內。當電路遭到大於本製程可容許之偏壓加壓一段時間(應力實驗),可以量測到加壓五個小時內,鎖定範圍與除頻範圍之衰減。量測應力後鎖定範圍的結果與未加壓的電路比較有想當明顯的變化。在本段將討論熱載子效應對注入鎖定除頻器之鎖定範圍的影響。
最後,我們探討在一個除二注入鎖定除頻器上的熱載子效應。利用台灣積體電路公司(TSMC)之0.18 微米製程完成。本電路直接經由金屬氧化半導體電晶體注入外部訊號耦合到串聯共振腔內。本段可以見到應力之後與應力之前電路的鎖定範圍之衰減與振盪頻率的變化,還有注入訊號與鎖定訊號的相位雜訊皆上升。


First, the thesis presents a novel wide locking range divide-by-4 injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-4 ILFD uses a cross-coupled voltage-controlled oscillator (VCO) with a parallel-tuned LC resonator and an active-passive composite to serve as an injection device with the function of nonlinear mixer. At the drain-source bias of 0.8 V, and at the incident power of 0 dBm the operation range of the divide-by-4 is 2.2 GHz, from the incident frequency 10.5 GHz to 12.7 GHz, the percentage is 18.96%. The locking range of the divide-by-4 is 1.6 GHz, from the incident frequency from 10.6 GHz to 12.2 GHz, the percentage is 14.035%. The core power consumption is 10.6 mW. The die area is 0.492×0.819 mm2.
Secondly, we discuss the effect of ac hot-carrier stress on the performance of a wide locking range divide-by-4 injection-locked frequency divider (ILFD). The ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process. The ILFD uses direct injection MOSFETs for coupling external signal to the resonators. It is shown that the locking range, operation range decrease with stress time. after RF stress at an elevated supply voltage for 5 hours have been examined by experiment. The measured locking range after RF stress shows significant degradation from the fresh circuit condition. Impact of hot carrier effect on the ILFD’s locking range is discussed.
Finally, we investigates hot carrier (HC) effect on a divide-by-2 injection-locked frequency divider (ILFD). The ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process. The ILFD uses direct injection MOSFETs for coupling external signal to the series-resonant resonator. It is shown that the locking range decreases and the oscillation frequency with stress time, and the phase noise in both the free-running and locked state increases with stress time. The measured operation range after RF stress also shows degradation from the fresh circuit condition.

摘要 I Abstract III 誌謝 V Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 4 Chapter 2 Overview of the Voltage Controlled Oscillators 5 2.1 Introduction 5 2.2 Basic Theory of Oscillators 6 2.2.1 Feedback Oscillators 6 2.2.2 Negative Resistance 11 2.3 Parallel RLC Tank 13 2.3.1 Quality Factor in LC Resonator Circuit 13 2.3.2 Inductor Design 17 2.3.3 Transformer Design 24 2.3.4 Varactor Design 33 2.4 Important Parameters of VCO 39 2.4.1 The VCO Frequency [Hz] : 39 2.4.2 Power Dissipation [mW] & Output Power[dbm]: 39 2.4.3 The VCO Tuning Sensitivity [Hz/V]: 40 2.4.4 The Phase Noise(PN) of VCO [dBc/Hz] : 42 2.4.5 Figure-of-Merit (FOM) [dBc/Hz]: 47 2.5 Overview of the Cross-Coupled Oscillator 48 Chapter 3 Principles and Design Concepts of Injection Locking Frequency Divider 52 3.1 Principle of Injection Locked Frequency Divider 53 3.2 Locking Range 55 3.3 Direct ILFD 58 Chapter 4 LC Divide-by-4 Injection-Locked Frequency Divider Using Two Linear Mixers 59 4.1 Introduction 59 4.2 Circuit Design 62 4.3 Measurement Results 66 Chapter 5 Effects of Hot-Carrier Stress on the RF Performance of a 0.18μm MOS Divide-by-4 LC Injection-Locked Frequency Divider 68 5.1 Introduction 68 5.2 Circuit Design 71 5.3 Measurement Results 73 Chapter 6 Experimental Evaluation of Hot-Carrier Stressed Series-Tuned Injection-Locked Frequency Divider 78 6.1 Introduction 78 6.2 Circuit Design 81 6.3 Measurement Results 83 Chapter 7 Conclusion 96 References 98

[1] N. M. Nguyen and R. G. Meyer, “Start-up and frequency stability in high-frequency oscillators,” IEEE J. Solid-State Circuit, vol. 27, no. 5, pp. 810–820, May 1992.
[2] B.Razavi, RF Microelectronics, Prentice Hall PTR 1998.
[3] B. Razavi, Design of Analog CMOS Integrated Circuits, Mc Graw Hill, 2001.
[4] Adel S. Sedra and Kenneth C. Smith, Microelectronic Circuit fifth edition, Oxford, 2004
[5] J. Aguilera, and R. Berenguer, “Design and test of integrated inductors for RF applications,” Kluwer Academic Publishers, 2004.
[6] J. Craninckx, and M. S. J. Steyaert, “A fully integrated CMOS DCS-1800 frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2054-2065, 1998.
[7] Y. K. Koutsoyannopoulos, and Y. Papananos, “Systematic analysis and modeling of integrated inductors and transformers in RF IC design,” IEEE Trans.
Crcuits and System-II, vol. 47, no. 8, pp. 699-713, 2000.
[8] A . Zolfaghari, A. Chan, and B. Razavi, “Stacked inductors and transformers in CMOS technology,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 620-628, 2001.
[9] Y. Koutsoyannopoulos, “Novel Si integrated inductor and transformer structure for RF IC design,” Proc. ISCAS ‘99, vol. 2, pp. 573.576, 1999.
[10] C. Tang, C. Wu, and S. Liu, “Miniature 3-D inductors in standard CMOS process,” IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 471-480, 2002
[11] H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,” IEEE Trans. on Parts, Hybrids and Packaging, vol. PHP-10, no.2, pp. 101-109,, 1974.
[12] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J. olid-State Circuits, vol. 35, pp. 1368-1382, Sept. 2000.
[13] M. W. Geen, G. J. Green, R.G. Arnold, J. A. Jenkins, and R. H. Jansen, “Miniature multilayer spiral inductors for GaAs MMICs,” Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, pp. 303-306, Oct. 1989.
[14] A. Kiranas and Y. Papanaos, “Design issues towards the integration of passive components in silicon RF VCOs,” IEEE International Conference on Electronics, Circuits and Systems, vol. 2, pp. 311-314, Sept. 1998.
[15] P. Andreani, and S. Mattisson, “On the use of MOS varactors in RF VCOs,” IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 905-910, June 2000.
[16] D. Hauspie, E.-C. Park, and J. Craninckx, “Wide-band VCO with simultaneous switching of frequency band, active core, and varactor size,” IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1472–1480, Jul. 2007.
[17] J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/ 129 prescaler in 0.7 um CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, July 1996.
[18] J. Tang and D. Kasperkovitz, Oscillator Design Efficiency: A New Figure Of Merit For Oscillator Benchmarking.
[19] T. Lee and A. Hajimiri, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 326-336, Mar. 2000.
[20] D. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of the IEEE, vol. 54, pp. 329-330, Feb. 1966.
[21] A. Hajimiri and T. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 717–724, May 1999.
[22] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998.
[23] Behzad Razavi Design of Integrated Circuits for Optical Communications, Mc Graw Hill.
[20] D. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of the IEEE, vol. 54, pp. 329-330, Feb. 1966.
[21] A. Hajimiri and T. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 717–724, May 1999.
[22] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998.
[23] Behzad Razavi Design of Integrated Circuits for Optical Communications, Mc Graw Hill.
[24] S. H. Lee, S. L. Jang, and Y. H. Chung, “A low voltage divide-by-4 injection
locked frequency divider with quadrature outputs,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 5, pp. 373–375, May 2007.
[25] K. Yamamoto and M. Fujishima, “70 GHz CMOS harmonic injectionlocked divider,” in IEEE Int. Solid-State Circuits Conf. Dig., pp. 2472–2481, Feb. 2006.
[26] S.-L. Jang, C.-H. Liu, C.-W. Chang, and M.-H. Juang, " A low voltage, low power divide-by-4 LC-tank injection-locked frequency divider, " Int. J. Electronics., vol. 98, no. 4, pp. 521-527, April 2011.
[27] S.-L. Jang, C. C. Liu and C.-W. Chung, ” A tail-injected divide-by-4 SiGe HBT injection locked frequency divider,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 4, pp. 236-238, April 2009.
[28] S.-L. Jang, C.-C. Liu, and J.-F. Huang, ” Divide-by-3 injection-locked frequency divider using two linear mixers,” IEICE Trans. on Electron., vol. E93-C, no.1, pp. 136-139, Jan. 2010.
[29] S.-L. Jang, H.-S. Chen, C.-C. Liu, and M.-H. Juang” A 0.35 μm CMOS Divide-by-3 LC injection locked frequency divider using linear mixers,” Micro. and Opt. Tech. Lett., vol. 52, no. 12, pp. 2740-2743, Dec., 2010.
[30] S.-L. Jang, and C.-W. Chang, ” A 90nm CMOS LC-tank divide-by-3 injection-locked frequency divider with record locking range,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 4, pp. 229-231, April 2010.
[31] S.-L. Jang, Y.-S. Chen, C.-W. Chang, and C.-C. Liu, ” A wide-locking range ÷3 injection-locked frequency divider using linear mixer,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 7, pp. 390-392, July 2010.
[32] M.-C. Chuang, J.-J. Kuo, C.-H.Wang, and H. Wang, ”A 50 GHz divide-by-4 injection lock frequency divider using matching method’, IEEE Microw. Wireless Compon. Lett., vol. 18, no. 5, pp. 344–346, May 2008.
[33] E. Takeda, C. Y. Yang, and A. Miura-Hamada, Hot-Carrier Effects in MOS Devices. New York: Academic, 1995.
[34] S.-S. Liu, S.-L. Jang, and C.-G. Chyau, " Compact LDD nMOSFET degradation model," IEEE Trans. Electron Devices, Vol. 45, No. 7, pp.1538-1547, 1998.
[35] J.-H. Lee, S.-Y. Kim, I. Cho, S. Hwang, and J.-H. Lee,” 1/f noise characteristics of sub-100 nm MOS transistors,” J. Semicond. Technol. Sci., vol. 6, no. 1, pp. 37–41, Mar. 2006.
[36] S. Naseh, M. J. Deen, and O. Marinov, “Effects of hot-carrier stress on the performance of the LC-tank CMOS oscillator,” IEEE Trans. Electron Devices, pp. 1334-1339, 2003.
[37] T. Quemerais, L. Moqoillon, V. Huard, I. M. Fournier, P. Benech, N. Corrao, and X. Mescot, “Hot-carrier stress effect on a CMOS 65-nm 60-GHz one-stage power amplifier,” IEEE El Dev Lett 31:927 (2010).
[38] S. Naseh, M. J. Deen, and C. H. Chen, “Effects of hot-carrier stress on the performance of CMOS low-noise amplifiers”, IEEE Trans. Device and Materials Reliability, vol. 5, no. 3, pp. 501-508, Sep. 2005.
[39] Y. Leblehici and S-M Kang; “Hot-Carrier Reliability of MOS VLSI Circuits,” Kluwer Academic Publisher, 1993.
[40] C. Hu, S. C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, and K. W. Terrill, “Hot-electron-induced MOSFET degradation—Model, monitor, and improvement,” IEEE J. Solid-State Circuits, vol. SSC-20, no. 1, pp. 295–305, Feb. 1985.
[41] H. R. Rategh and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813–821, June 1999.
[42] Y.-H. Chuang, S.-H. Lee, R.-H. Yen, S.-L. Jang, J.-F. Lee and M.-H. Juang, “A wide locking range and low voltage CMOS direct injection-locked frequency divider,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 5, pp. 299-301, May 2006.
[43] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1170 – 1174, July 2004.
[44] Y. Shen, J. Lee, and H. Shin, “Hot carrier stress effect on the performance of 65 nm CMOS low noise amplifier,” in IEEE ICICDT, Austin, TX, May 2009, pp. 249–252.
[45] S.-L. Jang, J.-S. Yuan, S.-D. Yen, H.-S. Tang, S.-Y. Chen, G.-W. Huang , “Experimental evaluation of hot electron reliability on differential Clapp-VCO”, Microelectronics Reliability, pp. 254–258, Feb. 2013.
[46] C. Salm, E. Hoekstra, J. S. Kolhatkar, A. J. Hof, H. Wallinga, and J, Schmitz , “Low-frequency noise in hot-carrier degraded nMOSFETs”, Microelectronics Reliability, pp. 577–580, 2007.
[47] L. Negre, D. Roy, S. Boret, P. Scheer1, D. Gloria, and G. Ghibaudo, “ Advanced 45nm MOSFET small-signal equivalent circuit aging under DC and RF hot carrier stress,” IEEE, Int. Reliability Physics Symposium (IRPS), 2011, pp.: HV.1.1 - HV.1.4
[48] C. Dai, S.V. Walstra, S.-W. Lee, “The effect of instrinc capacitance degradation on circuit performance,” Symp. VLSI Technology, 1996, 196-197.
[49] C. H. Ling, D. S. Ang, and S. E. Tan, “Effects of measurement frequency and temperature anneal on differential gate capactitance spectra observed in hot carrier stressed MOSFETs,” IEEE Electron Devices, pp. 1528-1535, 1995.
[50] J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/ 129 prescaler in 0.7 um CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, July 1996.
[51] Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOScircuits for gigahertz single-phase clocks,” IEEE J. Solid-State Circuits, vol. 31, pp. 456-463, Mar. 1996
[52] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18-um CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, Apr. 2004.
[53] H. R. Rategh, and T.H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, pp. 813-821, June 1999.
[54] H. D. Wohlmuth and D. Kehrer, “A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 823-826, Sept. 2002.
[55] M. Tiebout, “A 480 uW 2 GHz ultra low power dual-modulus prescaler in 0.25 um standard CMOS,” IEEE International Symposium on Circuit and System (ISCAS), vol. 5, pp. 741-744, May 2000.
[56] H. Wu, and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement,” IEEE ISSCC Dig. Tech. Papers, pp. 412-413, Feb. 2001.
[57] R. J. Betancourt-Zamora, S. Verma, and T. H. Lee, “1 GHz and 2.8 GHz CMOS injection- locked ring oscillator prescalers,” IEEE Symposium on VLSI Circuits, pp. 47-50, June 2001.
[58] P. Kinget, R. Melville, D. Long, and V. Gopinathan, “An Injection Locking Scheme for Precision Quadrature Generation,” IEEE J. Solid-State Circuits, vol. 37, pp. 845-851, July 2002.
[59] W. Z. Chen, and C. L. Kuo, “18 GHz and 7 GHz superharmonic injection-locked dividers in 0.25pm CMOS technology,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 89-92, Sept. 2002.
[60] H. Wu, “Signal generation and processing in high-frequency/high-speed silicon-based integrated circuits,” PhD thesis, California Institute of Technology, 2003.
[61] R. Adler, “A study of locking phenomena in oscillators,” Proc. IEEE, vol. 61, pp.1380-1385, Oct. 1973.
[62] Y.-A. Liu and C. Y. Cao “Noise mechanism of drain avalanche hot carrier stress in scaled MOSFE”, ISECS, (2010) pp. 256-259.
[63] B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J. Solid-State Circuits, (1996) vol. 31, no. 3, pp. 331-343.

無法下載圖示 全文公開日期 2018/07/26 (校內網路)
全文公開日期 本全文未授權公開 (校外網路)
全文公開日期 本全文未授權公開 (國家圖書館:臺灣博碩士論文系統)
QR CODE