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研究生： 陳韋旗
Wei-Chi Chen
論文名稱： 新式注入鎖定除頻器及電壓控制振盪器之設計
Design of Novel Injection-Locked Frequency Dividers and Voltage-Controlled-Oscillators
指導教授： 張勝良
Sheng-Lyang Jang
口試委員: 徐敬文
Ching-Wen Hsue
黃進芳
Jhin-Fang Huang
鄧恆發
Heng-Fa Teng
莊昀學
Yun-Hsueh Chuang
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2008
畢業學年度： 96
語文別： 英文
論文頁數： 139
中文關鍵詞： 四相位電壓控制振盪器 、電壓控制振盪器 、注入鎖定除頻器 、互補式金氧半導體
外文關鍵詞： QVCO, ILFD, VCO, CMOS
相關次數： 點閱：197  下載：3 
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    • 壓控振盪器與除頻器是頻率合成器電路中主要的電路之一。對壓控振盪器而言，低相位雜訊可避免相鄰雜訊訊號經由混波轉換的干擾。而振盪器的輸出則經由除頻器來達成降頻的工作，因此，除頻器需具有高頻操作，寬的操作頻寬及低功率消耗。
    首先，本論文呈現兩個除三直接注入鎖定除頻器。第一個電路裡，在電源1.6V量測到頻率可調範圍從2.17GHz到2.43GHz，注入功率大小為0dBm的訊號時鎖定範圍高達1.03GHz(14.9%)，從6.41GHz到7.44GHz，功率消耗15.1mW，晶片面積為0.753 × 0.786mm2。第二個電路裡，在電源1.0V時其頻率可調範圍由7.10GHz至7.72GHz，操作在7.04 GHz 頻帶其注入鎖定後在10KHz偏移頻率下，此振盪器具有低於-111.52 dBc/Hz的相位雜訊表現，功率消耗為2.46mW。
    其次，我們呈現CMOS LC克萊柏電壓控制振盪器及串聯可調除二直接注入鎖定除頻器。在克萊柏電壓控制振盪器裡，電源1.4V時操作在5.297 GHz 頻帶在1Hz偏移頻率下的相位雜訊為-187.1 dBc/Hz。電路的功率消耗為3.78mW，可調電壓由0V至1.4V，可調範圍從4.58 GHz至5.62 GHz約為1.04 GHz，晶片面積為0.556 × 0.604 mm2。串聯可調除二直接注入鎖定除頻器電路裡，在電源1.5V時其頻率可調範圍由5.48GHz至6.36GHz，注入功率大小為0dBm的訊號時鎖定範圍高達3.39GHz(28.17%)，從10.34GHz到13.73GHz，功率消耗4.94mW，晶片面積為0.574 × 0.573mm2。
    最後，一個利用動態門檻電壓電晶體技巧之新式四相位壓控振盪器亦呈現，此技巧將降低電源電壓以至減低功率的消耗。在電源1.5V時操作在4.94 GHz 頻帶在1Hz偏移頻率下的相位雜訊為-114.23 dBc/Hz，且FoM為-178.3 dBc/Hz.，功率消耗為8.1mW。可調電壓由0V至1.5V，可調範圍從4.49 GHz至5.16 GHz約為670 MHz，晶片面積為0.97 × 0.97 mm2。

    The key building blocks in the frequency synthesizer are the voltage controlled oscillator (VCO) and the high frequency divider circuit. Most importantly, low phase-noise is required to avoid corrupting the mixer-converted signal by close interfering tones for VCO circuit. The output of the VCO is divided down by the frequency divider which requires operating at high frequencies, wide operating range and lower power consumption.
    Firstly, this thesis describes two divider-by-3 LC-tank injection locked frequency dividers. In the first circuit, at the supply voltage of 1.6V, the divider free-running frequency is tunable from 2.17 to 2.43 GHz, and at the incident power of 0 dBm the locking range is about 1.03 GHz (14.9%), from the incident frequency 6.41 to 7.44GHz. The core power consumption is 15.1mW. The die area is 0.753 × 0.786 mm2. The second circuit measurement results show that at the supply voltage of 1.0 V, the free-running ILFD is tunable from 7.10 to 7.72 GHz. The locked output phase noise is -111.52 dBc/Hz at 10-KHz offset frequency from the7.04GHz. The core power consumption is 2.46 mW at the supply voltage of 1.0V.
    Then the CMOS LC-tank Clapp voltage controlled oscillator and series-tuned divider-by-2 injection locked frequency divider. In CMOS LC-tank Clapp VCO, at the supply voltage of 1.4V, the output phase noise of the VCO is -118.43 dBc/Hz at 1MHz offset frequency from the carrier frequency of 5.297 GHz, and the figure of merit is -187.1 dBc/Hz. The power consumption of VCO core is 3.78 mW. Tuning range is about 1.04 GHz, from 4.58 GHz to 5.62 GHz, while the control voltage was tuned from 0V to 1.4 V. The die area is 0.556 × 0.604 mm2. In series-tuned divider-by-2 ILFD, the measurement results show that at the supply voltage of 1.5 V, the divider free-running frequency is tunable from 5.48 to 6.36 GHz, and at the incident power of 0 dBm the locking range of the divide-by-2 ILFD is about 3.39 GHz (28.17%), from the incident frequency 10.34 to 13.73GHz. The core power consumption is 4.94 mW. The die area is 0.574 × 0.573 mm2.
    Finally, a novel quadrature VCO (QVCO) is proposed. By using dynamic threshold voltage MOS technique, it can reduce supply voltage and power consumption. At the supply voltage of 1.5V, the output phase noise of the QVCO is -114.23 dBc/Hz at 1MHz offset frequency from the carrier frequency of 4.94 GHz, and the figure of merit is -178.3 dBc/Hz. The power consumption of QVCO core is 8.1 mW. Tuning range is about 670 MHz, from 4.49 GHz to 5.16 GHz, while the control voltage was tuned from 0V to 1.5 V. The die area is 0.97 × 0.97 mm2.

    中文摘要 I Abstract III 誌謝 V Table of Contents VI List of Figures VIII List of Tables XIII CHAPTER 1 INTRODUCTION 1 1.1 BACKGROUND 1 1.2 THESIS ORGANIZATION 4 CHAPTER 2 OVERVIEWS OF VOLTAGE-CONTROLLED OSCILLATORS 6 2.1 INTRODUCTION 6 2.2 THE OSCILLATOR THEORY 7 2.3 SORTS OF OSCILLATORS 11 2.3.1 RESONATORLESS OSCILLATORS 11 2.3.2 LC-TANK OSCILLATORS 14 2.4 DESIGN CONCEPTS OF VOLTAGE-CONTROLLED OSCILLATORS 16 2.4.1 VCO CHARACTERISTIC PARAMETERS 18 2.4.2 PHASE NOISE IN OSCILLATOR 20 2.5 Parallel RLC Tank 28 2.5.1 QUALITY FACTOR 29 2.5.2 INDUCTOR AND TRANSFORMER 32 2.5.3 CAPACITORS AND VARACTORS 49 2.5.4 RESISTORS 58 CHAPTER 3 DIVIDER-BY-3 LC-TANK INJECTION LOCKED FREQUENCY DIVIDER 60 3.1 INTRODUCTION 60 3.2 DIVIDE-BY-3 ILFD WITH INDUCTOR OVER MOS TOPOLOGY 62 3.2.1 DESIGN CONCEPT AND OPERATION OF ILFD BY 3 62 3.2.2 MEASUREMENT RESULTS 76 3.3 LOW-POWER DIVIDE-BY-3 ILFD 82 3.3.1 DESIGN CONCEPT OF LOW-POWER DIVIDE-BY-3 ILFD 82 3.3.2 MEASUREMENT RESULTS 84 CHAPTER 4 A CMOS LC-TANK CLAPP VOLTAGE CONTROLLED OSCILLATOR 88 4.1 INTRODUCTION 88 4.2 DESIGN CONCEPT AND OPERATION OF LC-TANK VCO 89 4.3 DESIGN OF THE TRANSFORMER 92 4.4 MEASUREMENT RESULTS 94 CHAPTER 5 DESIGN OF DIVIDER-BY-2 INJECTION LOCKED FREQUENCY DIVIDER 99 5.1 PRINCIPLE OF INJECTION LOCKED DIVIDER 100 5.1.1 LOCKING RANGE 102 5.2 DESIGN CONCEPT OF X-BAND SERIES-TUNED DIVIDER-BY-2 ILFD 105 5.3 MEASUREMENT RESULTS 109 CHAPTER 6 A CMOS COMPLEMENTARY COLPITTS QUADRATURE RING VCO 114 6.1 INTRODUCTION 114 6.2 TRADITIONAL QVCO CIRCUIT DESIGN 115 6.3 TRADITIONAL QUADRATURE CMOS VCO DESIGN 117 6.4 DESIGN CONCEPT OF CMOS QUADRATURE RING VCO 122 6.4.1 DYNAMIC THRESHOLD VOLTAGE MOS (DTMOS) 124 6.5 MEASUREMENT RESULTS 126 CHAPTER 7 CONCLUSION 131 REFERENCES 134

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