以Logical Effort為基礎之快速CMOS 電路設計軟體工具｜國立臺灣科技大學博碩士論文系統

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研究生：	曾峪鴻 Yuh-hom Tseng
論文名稱：	以Logical Effort為基礎之快速CMOS 電路設計軟體工具 A Logical-effort-based Software Tool for Designing Fast CMOS Circuits
指導教授：	吳乾彌 Chen-Mie Wu
口試委員:	陳郁堂 Yie-Tarng Chen 張勝良　 Sheng-Lyang Jang
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	62
中文關鍵詞：	cmos電路
外文關鍵詞：	logical effort, cmos circuit
相關次數：	點閱：329 下載：5
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上一筆

本論文是以Logical Effort Method為基礎，並使用C語言來實現其相關之軟體工具，以幫助設計快速CMOS電路，相關的研究可分為: Logical Effort Method的理論描述、如何以C語言來實現Logical-effort-based軟體工具、如何以Logical-effort-based軟體工具來設計快速CMOS電路等。最後，使用含單支或多支之CMOS電路來驗證Logical-effort-based 軟體工具之功能，並以輸出結果展示其計算CMOS電路各邏輯閘的最佳尺寸和路徑最小延遲之能力。

This thesis is based on the logical effort method and, by using C language, a software tool has been implemented which can help designing fast CMOS circuits. The related research work includes studying the logical effort method, using C language to realize the logical-effort-based software tool, and using the logical-effort-based software tool to design fast CMOS circuits. Finally, CMOS circuits with one- or multi-way branches are used to verify the function of the logical-effort-based software tool. Meanwhile, the output results also show that the software tool can compute the minimum delay along a path in a CMOS circuit and find the optimal transistor sizes for the related logical gates.

Chapter 1 Introduction
1.1 Background	1
1.2 Thesis Structure and Scope	1
Chapter 2 Logical Effort Method for Designing Fast CMOS Circuits
2.1 MOS Transistor Theory	3
2.1.1 MOSFET Model	3
2.1.2 CMOS Inverter Model	8
2.2 Logic Effort of CMOS Logic Gates	10
2.2.1 Delay in a CMOS Logical Gate	10
2.2.2 Logical Effort of CMOS Logical Gates	12
2.3 The Logical-effort-based Method for Minimizing the Delay along a Path	15
Chapter 3 Design of a Logical-effort-based Software Tool
3.1 Design Flow of the Software Tool	19
3.2 Structure and Implementation of the Software Tool	23
Chapter 4 Testing and Verification of the Logical-effort-based Software Tool
4.1 Multistage Circuits with One-way Branches	34
4.2 Multistage Circuits with Multi-way Branches	39
Chapter 5 Conclusions	46
References 	47

                                

[1] I. Sutherland, B. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann, 1999.
[2] Neil .E. Weste and David Harris, CMOS VLSI Design, 3rd ed., Addison Wesley, 2005.
[3] A. Kabbani, D. Al-Khalili, and AJ Al-Khalili, ”Delay Analysis of CMOS Gates Using Modified Logical Effort Model,” IEEE transactions on Computer –Aided Design of Integrated Circuits and Systems, Vol. 24, No. 6, June 2005.
[4] John Keane and Hanyong Eom, ”Subthreshold Logical Effort: A Systematic Framework for Optimal Subthreshold Device Sizing,” Design Automation Conference, pp. 425–428, 2006.
[5] Shrirang K. Karandikar and Sachin S Sapatnekar, “Logical Effect Based Technology Mapping,” Computer Aided Design, pp. 419 – 422, 2004.
[6] Behzad Razavi, Design of Analog CMOS Integrated Circuits, 1st ed., McGraw Hill, 2001.
[7] 施敏,張俊彥,半導體物理與製作技術,第二版,民國八十六年.
[8] S.M. Sze, Physics of Semiconductor Devices, 2nd ed., Wiley, New York, 1981.
[9] James W Nilsson, Susan A. Riedel, Electrical Circuit, 5th ed., Addison Wesley.
[10]吳讚宏,陳秋華, C程式語言入門與應用, 第一版, 民國九十一年十二月

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