本論文係使用TSMC 0.18 µm CMOS製程研製一型5 GHz疊接式低雜訊放大器及一型1-10 GHz 單端轉差動之低雜訊放大器。疊接式低雜訊放大器採用源極退化電感電路架構，以降低雜訊指數，其匹配網路以LC元件實現，該晶片量測結果在操作頻率5 GHz時，增益為14.67 dB、輸入反射損失為-16 dB及雜訊指數為2.87 dB。
單端轉差動之低雜訊放大器係將單端轉差動電路與寬頻低雜訊放大器結合，單端轉差動電路採用共閘極-共源極組態組成，具有超寬頻之特性及輸出平衡、雜訊抵消和無訊號失真之優點，低雜訊放大器則採用 型匹配架構，以增加操作頻寬，並將單端轉差動電路與低雜訊放大器整合於單一晶片中，該晶片量測結果在操作頻率1-10 GHz頻寬範圍內，增益為9.45~19.6 dB，反射損失為-7.7~-6 dB，訊指數為8.8~11.8 dB，差動輸出相位差為170~182度。

This thesis presents a 5 GHz cascode low noise amplifier and a 1-10 GHz single-ended to differential low noise amplifier. using TSMC 0.18 μm CMOS process. The cascode low noise amplifier employs the technique of source inductor degeneration to decrease the noise figure. The matching network of the amplifier is designed by the LC lumped elements. The developed low noise amplifier has a measured gain of 14.67 dB, a measured input return loss of 16 dB, and a measured noise figure of 2.87 dB at 5 GHz.
The single-ended to differential low noise amplifier combines the single-ended to differential circuit and two wideband low noise amplifiers. The single-ended to differential circuit employs a common gate-common source stage to achieve ultra-wide-band and advantages of the output balance, noise cancellation and distortion cancellation. The developed amplifier employs a matching circuit to enhance the bandwidth. Finally, the single-ended to differential circuit and wideband low noise amplifier are integrated in a single chip. The developed amplifier has a measured gain of 9.45~19.6 dB, a measured input return loss of -7.7~-6 dB, a measured noise figure of 8.8~11.8 dB, and a measured output phase difference of 170~182 degree, in the frequency range of 1-10 GHz.

[1] B. Razavi, RF Microelectronics, Upper Saddle River, NJ, USA: Prentice-Hall, 1998.
[2] S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts, and B. Nauta, “The BLIXER, a wideband balun-LNA-I/Q-mixer topology,” IEEE J. Solid-State Circuits, vol. 43, no. 12, Dec. 2008.
[3] J. Kim, J. S. Martinez, “Wideband inductorless balun-LNA employing feedback for low-power low-voltage applications,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 9, Sep. 2012.
[4] H. A. Haus et al., “Representation of noise in linear two ports,” Proc. IRE, vol. 48, pp. 69-74, Jan. 1960.
[5] S. P. Voinigescu et al., “A scalable high-frequency noise model for bipolar transistors with application optimal transistor sizing for low-noise amplifier design,” IEEE J. Solid-State Circuits, vol. 32, pp. 1430-1439, Sep. 1997.
[6] D. K. Shaeffer et al., “A 1.5 V, 1.5 GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, pp. 745-758, May 1997.
[7] P. Andreani et al., “Noise optimization of an inductively degenerated CMOS low noise amplifier,” IEEE Trans. Circuits Syst., vol. 48, pp.835-841, Sep. 2001.
[8] S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts, and B. Nauta, “Wideband balun-LNA with simultaneous output balancing, noise-canceling and distortion-canceling,” IEEE J. Solid-State Circuits, vol. 43, pp. 1341-1350, Jun. 2008.
[9] Y.-S. Lin, C.-C. Wang, G.-L. Lee, and C.-C. Chen, “High-performance wideband low-noise amplifier using enhanced -match input network,” IEEE Micro. Wireless Compon. Lett., vol. 24, no.3, Mar. 2014.
[10] P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th ed. New York: Wiley, 2001.
[11] Van Der Ziel, Noise in Solid-State Devices and Circuits. New York: Wiley, 1986.
[12] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 2004.
[13] K. B. Niclas, “The exact noise figure of amplifiers with parallel feedback and lossy matching circuits,” IEEE Trans. Microw. Theory Tech., vol. MTT-30, pp. 832-835, May 1982.
[14] F. Lin et al., “Design of MMIC LNA for 1.9 GHz CDMA portable communication,” in IEEE Microwave Millimeter-Wave Monolithic Circuits Symp., 1998, pp. 205-208.
[15] G. Knoblinger et al., “Thermal channel noise of quarter and sub-quarter micron NMOS FET’s,” in Proc. IEEE Microelectronic Test Structures Conf., 2000, pp. 95-98.
[16] J. K. Goo et al., “A noise optimization technique for integrated low noise amplifiers,” IEEE J. Solid-State Circuits, vol. 37, pp. 994-1002, Aug. 2002.
[17] T. K. Nguyen, C. H. Kim, G. J. Ihm, M. S. Yang, and S. G. Lee, “CMOS low-noise amplifier design optimization techniques,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 5, May 2004.
[18] S.-C. Tseng, C.-C. Meng, C.-H. Change, C.-K. Wu and G.-W. Hung, “Monolithic broadband Gilbert micromixer with an integrated marchand Balun using standard silicon IC process,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 12, pp. 4362-4371, Dec. 2006.
[19] K. Bult and H. Wallinga, “A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation,” IEEE J. Solid-State Circuits, vol. SC-22, no. 3, pp. 357-365, Jun. 1987.
[20] B. Nauta, “Single to differential converter,” U.S. Patent 5,404,050, Apr. 4, 1995, European Patent 92 20 38 39.3, Dec. 11, 1992.
[21] Y. S. Lin, J. F. Chang, and S. S. Lu, “Analysis and design of CMOS distributed amplifier using inductively-peaking cascaded gain cell for UWB systems,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 10, pp. 2513-2524, Oct. 2011.
[22] H.-W. Chiu, S.-S. Lu, and Y.-S. Lin, “A 2.17 dB NF, 5 GHz band monolithic CMOS LNA with 10 mW dc power consumption on a thin(20 ) substrate,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 3, pp. 813-824, 2005.