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研究生： 周賢仁
Hsien-Jen Chou
論文名稱： 雙共振氮化鎵製程與CMOS製程之除二注入鎖定除頻器設計
Dual-Resonance GaN HEMT and CMOS Divide-by-2 Injection-Locked Frequency Dividers
指導教授： 張勝良
Sheng-Lyang Jang
口試委員: 張勝良
Sheng-Lyang Jang
莊敏宏
Miin-Horng Juang
黃進芳
Jhin-Fang Huang
溫俊瑜
Jiun-Yu Wen
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2019
畢業學年度： 107
語文別： 英文
論文頁數： 142
中文關鍵詞： 注入鎖定除頻器 、氮化鎵製程 、雙共振
外文關鍵詞： Injection-Locked Frequency Divider, GaN HEMT, Dual-Resonance
相關次數： 點閱：245  下載：0 
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  •  上一筆

    • 近年來，隨著無線通訊系統快速發展，各種頻率合成器被研發出來，又以系統單晶片 (System-On-Chip)為主要趨勢。在整合各系統子電路時常出現操作時脈相位不同的情況，而導致輸出資料錯誤，因此需要鎖相迴路(Phase-Locked-Loop, PLL)來減少相位偏差，使得整合系統中各個子電路的時脈相位一致，減少輸出偏差。其內部包含了相位偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、壓控振盪器(VCO)、除頻器(FD)，而上述之中以壓控振盪器與除頻器為核心電路，因此本論文研究提出一氮化鎵製程之除頻器、兩種不同的CMOS製程除頻器。
    首先，我們探討一個使用穩懋半導體(win) 0.25μm GaN HEMT製程之除二注入鎖定除頻器。此注入鎖定除頻器是使用電容式交叉耦合對以及由一組互感電感與寄生電容的LC電路所組成。共振腔中，電感的部分由兩個互感電感所組成，目的在於可以耦合出雙頻的效果，進而擴增除頻器的可除頻範圍。在使用0.9V的供應電壓下，電流為2.16 mA，功率消耗為1.944 mW。由於GaN HENT為功率元件，此電路差動輸出信號在5.129 GHz的震盪頻率下能夠輸出5.93 dBm的輸出功率。在低注入功率時，此除頻器能夠有兩個分開的除頻範圍，在注入功率為0 dBm時，鎖定頻率範圍從10.11 GHz到11.62 GHz，此電路的面積為2×1 mm2。
    第二部分，我們設計一個使用台積電0.18 μm 1P6M CMOS之寬操作範圍的除二注入鎖定除頻器（ILFD）。此注入鎖定除頻器也是使用電容式交叉耦合對以及由電感與寄生電容的LC電路所組成。在不同的偏壓範圍條件下產生較寬的操作範圍，操作範圍為5GHz到12GHz，震盪頻率的調頻範圍為2.5 GHz到6 GHz。在使用1V的供應電壓下，電流為7.5 mA，功率消耗為7.5 mW，在注入功率為0 dBm時，鎖定頻率範圍3.8 GHz到12.7 GHz，晶片面積為1.06 × 1.2 mm2
    最後，我們設計一個雙頻的除二注入鎖定除頻器（ILFD）。此除頻器使用台積電0.18 μm 1P6M CMOS製程，晶片面積為0.933 × 0.993 mm2。此ILFD 由兩個子 ILFD所組成，有兩個非重疊的鎖定範圍，高頻段的鎖定頻率範圍為11.2 GHz到14.8 GHz，低頻段的鎖定頻率範圍為1.5 GHz到7 GHz。此兩組子ILFD在電感中都有加上可變電容，可以為調變頻率之作用。

    Recently, various frequency synthesizers have been developed with the rapid development of wireless communication systems in which SoC (System on a chip) is the main trend of them. When integrating the sub-circuits in system, there are phase error or clock skew which generate asynchronous phenomenon in different sub-circuit blocks that causing output data error started up. Therefore, we need a Phase-Locked-Loop (PLL) for reducing the phase and clock error to decrease the output data error. In the Frequency synthesizer, its blocks include Phase/Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF), Voltage Controlled Oscillator (VCO), and Frequency Divider (FD). Among of them, the Voltage Controlled Oscillator and Frequency Divider are the main circuits, so this thesis proposed the design GaN HEMT Injection-Locked Frequency Divider (ILFD), two kind of different CMOS ILFD.
    First of all, this thesis uses win semiconductor corp. 0.25 μm GaN HEMT technology to achieve an Injection-Locked Frequency Divider divide-by-2. The ILFD consists of a capacitive cross-coupled pair and an LC-tank consisted of one coupled inductor pair and parasitic capacitor. The inductor part in resonator consists of two mutual inductors, it can make the purpose that coupling a dual-band and it can improve the locking range. With the supply voltage of VDD = 0.9 V, the GaN ILFD current and power consumption are 2.16 mA and 1.944 mW, respectively. Because the GaN HEMT is a power device, the circuit can generate the differential output signals with 5.93 dBm output power at the oscillation frequency 5.129 GHz. At low injection power, the ILFD has two non-overlapped locking range, and at injection power Pinj =0 dBm it has only one locking range from 10.11 to 11.62 GHz. The ILFD with a die area 2×1 mm2.
    Secondly, this thesis study using a tsmc 0.18 μm 1P6M CMOS technology to achieve a wide-operation range Injection-Locked Frequency Divider divide-by-2. The ILFD consists of a capacitive cross-coupled pair and an LC-tank consisted of inductors and parasitic capacitor. With different bias voltage range, this ILFD can generate a wide-operation range, where the operation range is from 5 to 12GHz, and the tunning range of oscillation frequency is from 2.5 to 6 GHz. With the supply voltage of VDD = 1 V, the ILFD current and power consumption are 7.5 mA and 7.5 mW, respectively, and at injection power Pinj =0 dBm, the locking range is from 3.8 to 12.7 GHz. The ILFD with a die area 1.06×1.2 mm2.
    Finally, this thesis study using a tsmc 0.18 μm 1P6M CMOS technology to achieve a dual-band Injection-Locked Frequency Divider divide-by-2. The ILFD consists of a capacitive cross-coupled pair and an LC-tank consisted of inductors and parasitic capacitor. This ILFD consisted of two sub-ILFDs, and it has two non-overlapped locking range. The locking range of high frequency band is from 11.2 GHz to 14.8 GHz and the locking range of low band is from 1.5 GHz to 7 GHz. In the inductors of the both sub-ILFDs, there are two pairs varactor added, and they can change the oscillation frequency. The ILFD with a die area 0.933×0.993 mm2.

    中文摘要 I Abstract III 誌謝 V Table of Contents VI List of figures VIII Chapter 1 Introduction 1 1.1 Background 1 1.2 Thesis Organization 4 Chapter 2 Overview of Voltage-Controlled Oscillators 5 2.1 Introduction 5 2.2 The Oscillators Theory 7 2.2.1 Negative Resistance (One-Port) View 8 2.2.2 Feedback (Two-Port) View 11 2.3 Design Concepts of Voltage-Controlled Oscillator 13 2.3.1 Parameters of a Voltage-Controlled Oscillator 13 2.3.2 Phase Noise 17 2.3.3 Quality Factor 29 2.4 Classification of Oscillators 33 2.4.1 Ring Oscillator 33 2.4.2 LC-Tank Oscillator 38 2.5 Type of the LC Oscillator 42 2.5.1 Single Transistor Oscillator 43 2.5.2 One-Port Oscillator (Negative-Gm Oscillator) 46 2.5.3 Cross-Coupled Oscillator 50 2.6 Research in RLC-Tank 54 2.6.1 Resistors 55 2.6.2 Inductor 56 2.6.3 Transformer 65 2.6.5 Varactors 72 Chapter 3 Overview of Injection Locking Frequency Divider 76 3.1 Introduction 76 3.2 Principle of Injection Locked Frequency Divider 77 3.3 Locking Range 79 Chapter 4 Dual-Resonance GaN HEMT Divide-by-2 Injection-Locked Frequency Divider 82 4.1 Introduction 82 4.2 Circuit Design 83 4.3 Measurement and Discussion 86 4.4 Odd modulus ILFD 91 Chapter 5 Wide-Operation Range 2:1 LC-tank Capacitive Cross-Coupled Injection-Locked Frequency Divider 96 5.1 Introduction 96 5.2 Circuit Design 97 5.3 Measurement and Discussion 99 Chapter 6 Dual-Band 2:1 LC-tank Capacitive Cross-Coupled Injection-Locked Frequency Divider 105 6.1 Introduction 105 6.2 Detailed Circuit Design 107 6.3 Measurement and Discussion 109 Chapter 7 Conclusions 117 References 119

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