研究生: |
黃郁珊 YU-SHAN HUANG |
---|---|
論文名稱: |
Design of Duel-Mode MLC STT-RAM-based Cache Design of Duel-Mode MLC STT-RAM-based Cache |
指導教授: |
謝仁偉
Jen-Wei Hsieh |
口試委員: |
吳晉賢
Chin-Hsien Wu 陳雅淑 Ya-Shu Chen 黃元欣 Yuan-Shin Hwang 謝仁偉 Jen-Wei Hsieh |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 資訊工程系 Department of Computer Science and Information Engineering |
論文出版年: | 2019 |
畢業學年度: | 107 |
語文別: | 英文 |
論文頁數: | 59 |
中文關鍵詞: | 自旋記憶體 、快取記憶體 、讀取干擾 、寫入干擾 |
外文關鍵詞: | MLC STT-RAM, Last-level Cache, Read Disturbance, Write Disturbance |
相關次數: | 點閱:285 下載:0 |
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