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研究生: 黃郁珊
YU-SHAN HUANG
論文名稱: Design of Duel-Mode MLC STT-RAM-based Cache
Design of Duel-Mode MLC STT-RAM-based Cache
指導教授: 謝仁偉
Jen-Wei Hsieh
口試委員: 吳晉賢
Chin-Hsien Wu
陳雅淑
Ya-Shu Chen
黃元欣
Yuan-Shin Hwang
謝仁偉
Jen-Wei Hsieh
學位類別: 碩士
Master
系所名稱: 電資學院 - 資訊工程系
Department of Computer Science and Information Engineering
論文出版年: 2019
畢業學年度: 107
語文別: 英文
論文頁數: 59
中文關鍵詞: 自旋記憶體快取記憶體讀取干擾寫入干擾
外文關鍵詞: MLC STT-RAM, Last-level Cache, Read Disturbance, Write Disturbance
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1 Introduction 2 Background and Motivation 2.1 Single-Level Cell STT-RAM 2.2 Multi-Level Cell STT-RAM 2.3 Read Disturbance 2.4 Cell Mapping Method 2.5 Motivation 2.6 Related Work 3 Duel-Mode STT-RAM Cache 3.1 Write Reduction 3.1.1 Avoid Unnecessary Restore 3.1.2 Tag-only Write 3.2 Data Migration 3.2.1 Intra-line Swapping 3.2.2 Inter-line Swapping 3.2.3 Access Counter with Tracking 3.3 Mode Selection 3.3.1 Set Sampling 3.3.2 Second Chance 4 Performance Evaluation 4.1 Experiment Setup 4.2 Impact of Di erent Group Size 4.3 Miss-rate Comparison 4.4 Energy Consumption 4.5 Performance Comparison 4.6 Comparison of Access Counts 5 Conclusion

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