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研究生: 楊仕凡
Shih-Fan Yang
論文名稱: 基於FPGA平台的八通道相位陣列式超音波訊號產生器
8-ch Ultrasonic Signal Generator Based on FPGA
指導教授: 許孟超
Mon-Chau Shie
口試委員: 阮聖彰
Shanq-Jang Ruan
陳維美
Wei-Mei Chen
林淵翔
Yuan-Hsiang Lin
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2011
畢業學年度: 99
語文別: 中文
論文頁數: 95
中文關鍵詞: 相位陣列式超音波
外文關鍵詞: DDS, Phase Array ultrasonic
相關次數: 點閱:210下載:7
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本篇論文利用數位直接合成(Direct Digital Synthesis,DDS)技術,設計出一個八通道的陣列式超音控制器,使用者可以利用電腦軟體透過USB控制八通道中任一通道的頻率和相位,以實現超音波陣列的控制,本設計的頻率控制範圍為1-50MHz,控制的精確度可以達到0.116Hz,在相位控制能力可以達到0.22°的解析度。這個設計主要分為三個部份,DDS單元、FPGA控制單元及類比濾波放大器電路,在DDS單元中,本論文採用AD9959做為主要的元件。在控制單元方面,本論文採用FPGA做為控制的核心,FPGA可以提供使用者設計出各種客製化的功能,並且和單晶片相比,FPGA在未來的研究更容易完成多通道擴充及更方便加入其他的電子電路。最後是類比濾波放大器電路,主電路主要包含了二個二階的MFB低通濾波器、一個減法放大器及一個方波轉換比較器。本論文主要設計了控制器的電路原理圖,最後,本論文在模擬軟體(ModelSim和LTspice)中完成了FPGA的功能模擬和類比濾波放大器的電路模擬,並且最後製作出了此設計的印刷電路板。


The phase array ultrasonic technology is widely used in the recent ultrasonic applications. However, the multi channel signal generators for this purpose are large and expensive. This thesis reports a new design for using the DDS technology to generate 8-ch ultrasonic signal. There are three parts of this design including, the DDS part, FPGA part and amplifier part. In the DDS part, AD9959 chips are used for DDS function with synchronization capability. The FPGA part is used to implement the UART module, control and protocol module and AD9959 SPI controller module. The analog part consists of second order low pass filters, differential amplifier and squaring circuit. The simulation result shows our design is functional as the design goal. It can generate the output from 1-50 MHz and phase resolution of 0.022°. However, the design is not complete. The schematic design, PCB placement and route, FPGA logic function design and design simulation are complete. The soldering, circuit debugging, and real field try are still not complete.

中文摘要 I Abstract II 致謝 III 目錄 IV 圖索引 VI 表索引 IX 第一章 緒論 - 1 - 1.1 研究動機與目的 - 1 - 1.2 論文架構 - 3 - 第二章 相關知識 - 4 - 2.1 研究背景 - 4 - 2.2 Direct digital synthesis (DDS)晶片的選用 - 7 - 2.3 FPGA晶片選擇與開發系統介紹 - 19 - 第三章 本論文所設計系統架構介紹 - 21 - 3.1 本系統架構簡介 - 21 - 3.2 FPGA系統 - 23 - 3.3 DDS連接方法 - 38 - 3.4 類比電路設計 - 43 - 3.5 其他電路設計 - 46 - 3.6 電路板設計 - 47 - 第四章 系統測試與結果 - 49 - 4.1 UART單元測試 - 49 - 4.2 控制單元測試 - 52 - 4.3 AD9959串列通訊單元測試 - 55 - 4.4 Top Module整體模擬測試 - 59 - 4.5 低通濾波器結果 - 64 - 4.6 減法放大器結果 - 67 - 4.7 類比電路整體結果 - 68 - 第五章 結論與未來研究方向 - 72 - 5.1 結論 - 72 - 5.2 未來展望 - 74 - 參考文獻 - 75 - Appendix A: The schematics. - 78 -

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