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研究生： 楊立啟
Li-Chi Yang
論文名稱： 利用標準0.18-μm CMOS製程實現金屬輔助光柵耦合器
Realization of Metal-assisted Grating coupler on unmodified 0.18-μm CMOS process
指導教授： 李三良
San-Liang Lee
恒勇智
Yung-Chih Heng
口試委員: 徐世祥
Shih-Hsiang Hsu
洪勇智
Yung-Jr Hung
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2015
畢業學年度： 103
語文別： 中文
論文頁數： 110
中文關鍵詞： 互補式金氧半製程 、光柵耦合器 、金屬反射鏡 、光互連 、多晶矽波導。
外文關鍵詞： CMOS process, Grating coupler, Metal mirror, Optical interconnect, Polysilicon waveguide
相關次數： 點閱：263  下載：8 
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  •  上一筆

    • 近年來隨著雲端高速運算的高度需求，資料中心開始採用主動式光纖光纜以降低功耗、提升頻寬。而光電積體電路為重要的核心技術，為了大量生產以利未來光通訊的普及，並考慮建立國內晶圓廠製程設計套件於CMOS光電積體電路雛形，本論文設計金屬輔助光柵耦合器實現於標準0.18-μm CMOS製程，以建立基本的光訊號耦合介面。本論文同時成功地以標準0.18-μm CMOS製程實現金屬輔助光柵耦合器。所設計之光柵耦合器經由模擬設計，於相同工作週期0.46下，調整光柵週期980 nm及940 nm，可分別設計中心波長於1585 nm及1565 nm；耦合效率則分別為-2.5 dB及-3.0 dB。考慮標準CMOS製程架構，場氧化層於多晶矽層下方僅約450 nm，導致光場耦合至矽基板，而無法侷限光場於多晶矽層波導，故本論文使用後製程移除矽基板，驗證多晶矽層光互連的功能性。量測所得光柵中心波長約1585 nm及1565 nm，與設計值相當；耦合效率則分別為-4.0 dB及-5.3 dB；3 dB頻寬則皆約為70 nm。經金屬輔助反射鏡提升出光方向性後，成功提升耦合效率分別3.0 dB及2.6 dB。由回截方法估計波導傳輸損耗則為111.9 dB/cm，光柵耦合器之中心波長對角度敏感度則約為7.42 nm/degree。

    As applications of cloud computing services increase drastically, the demands of large capacity data centers make optical interconnects highly desired for connecting thousands of servers. The optical interconnects, like active optical cables, need to meet the requirements of low power consumption, low latency, compact, and large communication bandwidth. The optoelectronics integrated circuit (OIC) is the key technology to realize transceivers to meet the above requirements. In order to develop prototype process design kits for commercializing OICs using the standard CMOS process supported by semiconductor foundry, this thesis aims at realizing metal-assisted grating couplers with standard 0.18-μm CMOS process to build fundamental optical coupling I/O port interface.The proposed metal-assisted grating couplers can increase the coupling coefficient by recycling the downward diffracted light. They are designed and optimized with the optical waveguide simulation software. The grating coupler is designed to have the same duty cycle of 0.46 but different grating period of 980 nm and 940 nm for the center wavelength of 1585 and 1565 nm, respectively. The designed one-sided coupling efficiency is -2.5 dB and -3.0 dB for the two grating periods, respectively.The thickness of field oxide layer under the polysilicon layer for the standard CMOS process is only about 450 nm. This oxide layer is not thick enough to prevent the optical field guided in the polysilicon layer from leaking to the silicon substrate. Therefore, the silicon substrate was directly removed by post-process so that a well-confined optical interconnect functionality of the polysilicon layer could be verified and calibrated.For experimental demonstration, we have successfully realized metal-assisted grating coupler based on standard 0.18-μm CMOS process. For the grating couplers of 980-nm and 940-nm period, the measured one-sided coupling efficiency could achieve -4.0 dB at 1585 nm and -5.3 dB at 1565 nm, respectively. The Metal-assisted gratings can increase the coupling efficiency by 3.0 dB and 2.6 dB for the grating period of 980 nm and 940 nm, respectively. The optical waveguide transmission loss was estimated to be 111.9 dB/cm by using the cut-back method. When the incident angle to the grating coupler varies, the center wavelength of the grating coupler is shifted by 7.42 nm/degree.

    摘要 i Abstract ii 致謝 iii 目錄 iv 圖目錄 vi 表目錄 viii 第一章　研究動機與元件技術介紹 1 1-1 前言 1 1-2 研究動機 1 1-3 標準互補式金氧半架構介紹 3 1-4 電晶體閘極多晶矽架構 5 1-5 光耦合機制介紹 6 1-4 光柵耦合器發展現況 7 1-5 波導理論介紹 9 1-5-1司乃耳定律 9 1-5-2平面波導理論 10 1-6 光柵理論介紹 13 1-6-1布拉格定律 13 1-6-2光柵耦合器理論介紹 14 1-7 論文架構 16 第二章　光柵耦合器模擬設計 17 2-1 模擬方法介紹 17 2-1-1薄膜模態匹配法(Film Mode Match method, FMM) 17 2-1-2時域有限差分法(Finite-Difference Time-Domain, FDTD) 19 2-2 模擬模型架構設計 22 2-2-1光柵耦合器結構(Grating coupler structure) 22 2-2-2光纖光源結構(Fiber source structure) 23 2-3 光柵耦合器模擬設計 25 2-3-1順向耦合光柵耦合器設計 26 2-3-2順向耦合背面金屬輔助反射鏡設計 30 2-3-3反向耦合光柵耦合器設計 34 2-3-4反向耦合背面金屬輔助反射鏡設計 37 第三章　標準CMOS光電積體電路佈局 41 3-1 晶片佈局軟體平台 41 3-2 歷年光波導晶片下線 43 3-2-1 T18-101E-76+m 43 3-2-2 T18-102A-A0080+m 45 3-2-3 T18-102A-A0100+m 47 3-2-4 U18-102A-A0007+m 48 3-2-5 U18-103A-N0001+m 50 第四章　光電積體電路後製程 52 4-1 移除矽基板之後製程 53 4-2 移除Al-Cu金屬層之後製程 56 第五章　元件量測結果 58 5-1 量測系統架構 58 5-2 摻雜條件分析 61 5-3 波導傳輸損耗分析 63 5-4 光柵耦合器分析 66 5-4-1 順向耦合光柵耦合器 66 5-4-2 反向耦合光柵耦合器 71 5-4-3 光縮模器長度最佳化 73 5-4-4 調整耦合角度對中心波長的影響 76 5-5 光互連功能性確認 78 5-5-1 考慮被動反射式光柵波導濾波器驗證 78 5-5-2 考慮近遠紅外波段CCD相機驗證 82 第六章　結論與未來發展方向 84 6-1 成果與討論 84 6-2 未來發展方向 87 參考文獻 89 附錄A 光柵耦合器模組程式碼 98 附錄B 光纖光源結構模組程式碼 102 附錄C Cadence-Virtuoso佈局設計詳細步驟 103

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