在異質雙核心的嵌入式系統中, 行程交錯執行在汎用型處理器及特殊型處理器, 造成
(1) 子行程具有優先順序限制(2) 特殊型處理器的子行程為不可搶先式排程。此兩項特徵
大幅提高排程困難度。有別於以往的研究, 本研究將探討與分析異質雙核心處理器架構中,
如何評估排程器的實作成本, 如何以最低成本於核心間交換資料, 並探討行程的即時需求
與執行時間評估之技術問題。我們於Micrium uC/OS-II實現靜態與動態排程演算法, 以及
資源管理協定, 並將作業系統移植到異質雙核心的系統晶片(TI Davinci dm6446) 上, 增
加核心溝通模組, 使行程於雙處理器間進行溝通, 且於特殊型處理器中加入可搶先點概念
減少高優先權行程被阻擋時間。最後, 利用Motion JPEG的解碼實驗, 評估即時排程演算
法的可排程性, 以及執行時間量測之技術方法。

In heterogeneous dual-core embedded systems, subtasks of a task is executed interleaving
between a general purpose processor and a specific purpose processor, which
make (1) subtasks have precedence constraints, and (2) the subtask execution on a specific
purpose processor is non-preemptive. These two characters highly increase the difficulty
of scheduling problem. With a very different goal, this research presents the way to evaluate
the implementation cost of a scheduler and to exchange data with low cost between
cores on the heterogeneous dual-core processor architecture.
We implement resource synchronization protocols and static/dynamic priority scheduling
algorithms onMicrium uC/OS-II, and then port the uC/OS-II to a heterogeneous dualcore
System-on-Chip (TI Davinci DM6446). Tasks can communication with each other
between the two cores via the implemented inter-processor communication module. Furthermore,
we reduce blocking time of the high priority task by inserting preemption points
into tasks. Finally, we study the Motion JPEG decoder to evaluate the schedulability of
real-time scheduling algorithms, and to show the method of execution time measurement.

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