雙並聯四階共振腔之除二注入鎖定除頻器與除四Class-C注入鎖定除頻器的熱載子效應

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研究生：	張洲銘 Chou-Ming Chang
論文名稱：	雙並聯四階共振腔之除二注入鎖定除頻器與除四Class-C注入鎖定除頻器的熱載子效應 Divide-by-2 Injection-Locked Frequency Divider Implemented with Two Shunt 4th-Order Resonators and Hot-carrier Stress Effect on Divide-by-4 Class-C Injection-Locked Frequency Divider
指導教授：	張勝良 Sheng-Lyang Jang
口試委員:	莊敏宏 Miin-Horng Juang 徐敬文 Ching-Wen Hsue 賴文政 Wen-Cheng Lai
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2015
畢業學年度：	103
語文別：	英文
論文頁數：	87
中文關鍵詞：	壓控震盪器、除頻器、相位雜訊、除頻範圍
外文關鍵詞：	stress, lockded range
相關次數：	點閱：251 下載：0
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第一個電路是具有三個頻帶除二注入鎖定除頻器，使用TSMC 0.18 μm 1P6M CMOS製程，此注入鎖定除二除頻器使用交叉耦合的NMOS對和兩個並聯四階LC共振腔來形成一個六階共振腔具有三個共振頻率。測得的數據可顯示出注入鎖定除頻器可藉由固定偏壓條件下或可變電容的開關操作而具有三個鎖定範圍。

A three-band divide-by-2 LC injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-2 ILFD using a cross-coupled nMOS pair and two shunt 4th order LC resonators to form a 6th order resonator with three resonant frequencies. Measured data has shown the ILFD has three locking ranges at fixed bias condition or by varactor bias switching.

摘要			I
Abstract			III
誌謝			IIV
List of Contents	V
List of Figures	VII
List of Tables	XI
Chapter 1  Introduction	1
1.1 BACKGROUND	1
1.2 THESIS ORGANIZATION	3
Chapter 2  Design of Voltage Controlled Oscillators	4
2.1 INTRODUCTION	4
2.2 THE OSCILLATOR THEORY	5
2.3 QUALALITY FACTOR	8
2.4 SORTS OF OSCILLATORS	10
2.4.1 RESONATORLESS OSCILLATORS	11
2.4.2 LC-TANK OSCILLATORS	14
I. COLPITTS AND HARTLEY OSCILLATORS	14
II. NEGATIVE -GM OSCILLATORS	15
2.5 VARACTORS	17
2.5.1 JUNCTION VARACTORS	17
2.5.2 MOS VARACTORS	17
I. INVERSION-MODE PMOS VARACTOR (I-MOS)	19
II. ACCUMULATION-MODE PMOS VARACTOR (A-MOS)	20
2.6 INDUCTOR AND TRANSFORMERS	20
2.6.1 SPIRAL INDUCTOR	21
2.6.2 THE TRANSFORMER	27
2.7 DESIGN CONCEPTS OF VCO	32
2.7.1 VCO CHARACTERISTIC PARAMETERS	33
2.8 INJECTION LOCKING FREQUENCY DIVIDER	40
2.8.1 PRINCIPLE OF INJECTION LOCKED FREQUENCY DIVIDER	42
2.8.2 LOCKING RANGE	43
2.8.3 SWITCH ILFD	46
Chapter 3  Divide-by-2 Injection-Locked Frequency Divider Implemented  with Two Shunt 4th-order Resonators	48
3.1 INTRODUCTION	48
3.2 CIRCUIT DESIGN	50
3.3 MEASURED RESULTS	54
Chapter 4  Hot-carrier Stress Effect on Divide-by-4 Class-C Injection-Locked Frequency Divider	62
4.1 INTRODUCTION	62
4.2 CIRCUIT DESIGN OF THE PROPOSED ILFD	63
4.3 MEASUREMENT RESULTS	64
Chapter 5  A Dual-Resonance ÷3 Injection-Locked Frequency Divider	70
5.1 INTRODUCTION	70
5.2 CIRCUIT DESIGN	71
5.3 MEASUREMENT RESULTS	73
Chapter 6  Conclusions	80
References		82

                                

[1] J. Roggers, C. Plett, Radio Frequency Integrated Circuit Design, Artech House, 2003.
[2] B. Razavi, RF Microelectronics, Prentice Hall PTR, 1998.
[3] B. Razavi, “A study of phase noise in CMOS oscillators, ” IEEE J. Solid-State Circuits, vol. 31, p.p. 331-343 Mar. 1996.
[4] K. Shu, E. Sanchez-Sinencio, CMOS PLL Synthesizers : Analysis and Design, Springer, 2005.
[5] A. Porret, T. Melly, C. Enz, and E, Vittoz, “Design of high-Q varactors for low-power wireless applications using a standard CMOS process,” IEEE J. Solid-State Circuits, vol. 35, pp. 337-345, Mar. 2000.
[6] F. Svelto, P. Erratico, S. Manzini, and R. Castello, “A metal oxide semiconductor varactor,” IEEE Electron Device Lett., vol. 20, pp. 164-166, Apr. 1999.
[7] P. Andreani and S. Mattisson, “On the use of MOS varactors in RF VCO’s,” IEEE J. Solid-State Circuits, vol. 35, pp. 905-910, Jun. 2000.
[8] T. Soorapanth, C. Yue, D. Shaeffer, T. Lee, and S. Wong, “Analysis and optimization of accumulation-mode varactor for RF ICs,” in 1998 Symp. VLSI Circuits Dig. Tech. Papers, , pp. 22-23. Jun. 1998.
[9] J. Aguilera, and R. Berenguer, “Design and test of integrated inductors for RF applications,” Kluwer Academic Publishers, 2004.
[10] J. Craninckx, and M. S. J. Steyaert, “A fully integrated CMOS DCS-1800 frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2054-2065, 1998.
[11] Y. K. Koutsoyannopoulos and Y. Papananos, “Systematic analysis and modeling of integrated inductors and transformers in RF IC design,” IEEE Trans. Circuits and System-II, vol. 47, no. 8, pp. 699-713, 2000.
[12] A . Zolfaghari, A. Chan, and B. Razavi, “Stacked inductors and transformers in CMOS technology,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 620-628, Apr. 2001.
[13] Y. Koutsoyannopoulos, “Novel Si integrated inductor and transformer structure for RF IC design,” Proc. ISCAS , vol. 2, pp. 573-576, June. 1999.
[14] C. Tang, C. Wu, and S. Liu, “Miniature 3-D inductors in standard CMOS process,” IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 471-480, 2002
[15] H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,” IEEE Trans. on Parts, Hybrids and Packaging, vol. PHP-10, no.2, pp. 101-109, 1974.
[16] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J. Solid-State Circuits, vol. 35, pp. 1368-1382, Sept. 2000.
[17] P.-C. Huang, M.-D. Tsai, H. Wang, C.-H. Chen, and C.-S. Chang, “A 114GHz VCO in 0.13μm CMOS technology,” IEEE International Solid-State Circuits Conference, vol. 1, pp.404-606, 6-10 Feb. 2005.
[18] B. Razavi, Design of Analog CMOS Integrated Circuits, Mc Graw Hill, 2001.
[19] J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/ 129 prescaler in 0.7 um CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, July 1996.
[20] Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks,” IEEE J. Solid-State Circuits, vol. 31, pp. 456-463, Mar. 1996.
[21] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, Apr. 2004.
[22] H. R. Rategh, and T.H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, pp. 813-821, June 1999.
[23] H. D. Wohlmuth and D. Kehrer, “A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 823-826, Sept. 2002.
[24] M. Tiebout, “A 480 uW 2 GHz ultra low power dual-modulus prescaler in 0.25 um standard CMOS,” IEEE International Symposium on Circuit and System (ISCAS), vol. 5, pp. 741-744, May 2000.
[25] H. Wu, and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement,” IEEE ISSCC Dig. Tech. Papers, pp. 412-413, Feb. 2001.
[26] R. J. Betancourt-Zamora, S. Verma, and T. H. Lee, “1 GHz and 2.8 GHz CMOS injection- locked ring oscillator prescalers,” IEEE Symposium on VLSI Circuits, pp. 47-50, June 2001.
[27] P. Kinget, R. Melville, D. Long, and V. Gopinathan, “An Injection Locking Scheme for Precision Quadrature Generation,” IEEE J. Solid-State Circuits, vol. 37, pp. 845-851, July 2002.
[28] W. Z. Chen, and C. L. Kuo, “18 GHz and 7 GHz superharmonic injection-locked dividers in 0.25pm CMOS technology,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 89-92, Sept. 2002.
[29] H. Wu, “Signal generation and processing in high-frequency/high-speed silicon- based integrated circuits,” PhD thesis, California Institute of Technology, 2003.
[30] R. Adler, “A study of locking phenomena in oscillators,” Proc. IEEE, vol. 61, pp.1380-1385, Oct. 1973.
[31] S.-L. Jang , R.-K. Yang , C.-W. Chang and M.-H. Juang, "Multi-modulus LC injection-locked frequency dividers using single-ended injection", IEEE Microw. Wireless Compon. Lett.., vol. 19, pp. 311-313, 2009.
[32] Y.-H. Chuang, S.-H. Lee, R.-H. Yen, S.-L. Jang, J.-F. Lee and M.-H. Juang, “A wide locking range and low voltage CMOS direct injection-locked frequency divider,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 5, pp. 299-301, May 2006.
[33] H. Wu and A. Hajimiri, “A 19 GHz 0.5mW 0.35 μm CMOS frequencydivider with shunt-peaking locking-range enhancement,” in IEEE Int.Solid-State Circuits Conf., pp. 412-413, Feb. 2001.
[34] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State Circuits,vol. 39, no. 7, pp. 1170–1174, Jul. 2004.
[35] H. R. Rategh and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813–821, June 1999.
[36] S.-L. Jang, S.-S. Huang, J.-F. Lee and M.-H. Juang,” LC-tank Colpitts injection-locked frequency divider with record locking range,” IEEE Microw. Wireless Compon. Lett., pp.560-562, Aug. 2008.
[37] S. Lee, S. Jang, and C. Nguyen, “Low-power-consumption wide-locking-range dual-injection-locked 1/2 divider through simultaneous optimization of VCO loaded Q and current,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 10, pp. 3161–3168, Oct. 2012.
[38] S.-L. Jang, F.-B. Lin,and J.-F. Huang, ” Wide-band divide-by-2 injection-locked frequency divider using MOSFET mixers DC-biased in subthreshold region,” Int. J. Circ Theor App, 12, Jan. 2015.
[39] C.-W. Chang, S.-L. Jang, C.-W. Huang, and C.-C. Shih, " Dual-resonance LC-tank frequency divider implemented with switched varactor bias,” IEEE Int. VLSI- DAT, 2011, pp.1-4.
[40] S.-L. Jang, Z.-H. Wu, C.-W. Hsue and H.-F. Teng,” Wide-locking range dual-band injection-locked frequency divider,” Microw. Opt. Technol. Lett. vol. 55, 10, pp. 2333–2337, Oct. 2013.
[41] S.-L. Jang, L.-Y. Huang, C.-W. Hsue, and J.-F. Huang," Injection-locked frequency divider using injection mixer DC-biased in sub-threshold," IEEE Microw. Wireless Compon. Lett., vol. 25, no. 3, pp. 193-195, March 2015.
[42] S. Tam, P.-K. Ko, and C. Hu, “Lucky-electron model of channel hot-electron injection in MOSFET’s,” IEEE Trans. Electron Devices. Vol. ED-31, No. 9. p. 1116-1125, 1986
[43] S.-S. Liu, S.-L. Jang, and C.-G. Chyau, " Compact LDD nMOSFET degradation model, " IEEE Trans. Electron Devices, Vol. 45, No. 7, pp.1538-1547, 1998.
[44] S. H. Lee, S. L. Jang, and Y. H. Chung, “A low voltage divide-by-4 injection locked frequency divider with quadrature outputs,” IEEE Microw.Wireless Compon. Lett., vol. 17, no. 5, pp. 373–375, May 2007.
[45] S.-L. Jang, J.-F. Huang, C.-C. Fu and M.-H. Juang, ” Experimental evaluation of hot-carrier stressed series-tuned injection-locked frequency divider,” Analog Integr Circ Sig Process (2014) 80:133–139.
[46] S.-L. Jang, and J.-H. Hsieh, ”RF performance degradation in CMOS divide-by-3 injection-locked frequency divider due to hot carrier effects”, J. Low Power Electronics. Vol.9, No. 4, pp.484-489, Dec. 2013
[47] S.-L. Jang and T.-C. Fu, " Effects of hot-carrier stress on the RF performance of a 0.18μm MOS divide-by-4 LC injection-locked frequency divider," Fluct. Noise Lett. vol. 13, no. 2, 1450009-1 April, 2014.
[48] S.-L. Jang and C.-Y. Lin, ” A wide-locking range Class-C injection-locked frequency divider,” Electronics Letters .,vol. 50, 23, pp.1710-1712, 2014.
[49] B. Razavi, "A study of injection locking and pulling in oscillators," IEEE J. Solid-State Circuits, 39(9):1415-1424, Sept. 2004.
[50] K. Yamamoto and M. Fujishima, “70 GHz CMOS harmonic injection locked divider,” in IEEE Int. Solid-State Circuits Conf. Dig.,pp. 2472–2481, Feb. 2006.
[51] S.-L. Jang, C.-H. Liu, C.-W. Chang, and M.-H. Juang," A low voltage, low power divide-by-4 LC-tank injection-locked frequency divider, " Int. J. Electronics., vol. 98,no. 4, pp. 521-527, April 2011.
[52] S. L. Jang, Y. K. Wu, C. C. Liu, and J. F. Huang,“A dual-band CMOS voltage-controlled oscillator implemented with dual-resonance LC tank,” IEEE Microw. Wireless Compon. Lett.,, vol. 19, pp. 816-818, Dec.2009.
[53] Nikolay T. Tchamov, Svetozar S.Broussev, “Dual-Band LC VCO Architecture With a Fourth-Order Resonator” in IEEE Transactions on circuits and systems—II: Express Briefs, vol. 54, no. 3, March 2007.
[54] S.-L. Jang, Z.-H. Wu, C.-W. Hsue and H.-F. Teng,” Wide-locking range dual-band injection-locked frequency divider,” Microw. Opt. Technol. Lett. vol. 55, 10, pp. 2333–2337, October 2013
[55] S.-L. Jang, C.-W. Chang, J.-Y. Wun, and M.-H. Juang, ” Quadrature injection-locked frequency dividers using dual-resonance resonator,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 1, pp. 37-39, 2011.
[56] S.-L. Jang, L.-Y. Huang, C.-W. Hsue, and J.-F. Huang," Injection-locked frequency divider using injection mixer DC-biased in sub-threshold," IEEE Microw. Wireless Compon. Lett., vol. 25, no. 3, pp. 193-195, March 2015.
[57] H. Wu and L. Zhang, “A 16-to-18GHz 0.18μm epi-CMOS divide-by-3 injection-locked frequency divider,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp.27–29.
[58] S.-L. Jang, C.-W. Chang, C.-F. Lee, and J.-F. Huang, “Divide-by-3 LC injection locked frequency divider implemented with 3D inductors,” IEICE Trans. Electron., vol. E91-C, no. 6, pp. 956–962, Jun. 2008.
[59] S.-L. Jang, C.-Y. Lin, and C.-F. Lee, “A low voltage 0.35 μm CMOS frequency divider with the body injection technique,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 7, pp.470–472, July 2008.
[60] S.-L. Jang, C.-C. Liu, and J.-F. Huang, ” Divide-by-3 injection-locked frequency divider using two linear mixers,” IEICE Trans. on Electron., Vol.E93-C,No.1,pp.136-139, Jan. 2010.
[61] S.-L. Jang, and C.-W. Chang, ” A 90nm CMOS LC-tank divide-by-3 injection-locked frequency divider with record locking range,” IEEE Microw. Wireless Compon. Lett., vol. 20, pp.229-231, April, 2010.
[62] S.-L. Jang, Y.-S. Chen, C.-W. Chang, and C.-C. Liu, ” A wide-locking range ÷3 injection-locked frequency divider using linear mixer,” IEEE Microw. Wireless Compon. Lett., vol. 20, pp.390-392, July, 2010.
[63] S.-L. Jang, Y.-S. Chen, C.-W. Chang and C.-C. Liu,” injection-locked frequency dividing apparatus”, US patent # US008305116B2, 2012.
[64] Y.-T. Chen, M.-W. Li, H.-C. Kuo, T.-H. Huang, and H.-R. Chuang, “Low-voltage K-band divide-by-3 injection-locked frequency divider with floating-source differential injector,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 1, pp. 160–67, 2012.
[65] S.-L. Jang, and J.-H. Hsieh, ” A wide-locking range ÷3 injection-locked frequency divider using concurrent injection mechanisms,” Analog Integr Circ Sig Process, Vol. 77, Issue 3, pp 593-598., Dec. 2013.
[66] S.-L. Jang and C.-Y. Chuang, ” Wide-locking range ÷3 series-tuned injection-locked frequency divider,” Analog Integr Circ Sig Process, Vol. 76, 1, pp. 111-116., Jan. 2013.
[67] Jang S.-L., Lin C.-Y., and Juang M.-H., ” Enhanced locking range technique for a divide-by-3 differential injection-locked Frequency divider,” Electron. Lett., vol. 51, 19, pp. 456 – 458, 2015.
[68] S.-L. Jang, and C.-Y. Lin, ” Wide-locking range Class-C injection-locked frequency divider,” Electron. Lett.,vol. 50, 23, pp.1710-1712, 2015.

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