科技的飛速進步改變了我們的生活方式，帶來前所未有的便利和創新。新產品對於高頻的需求與日俱增，各種不同功能的電路與系統，在製程尺度微縮的影響和保持電路性能的前提下如何將其有效的整合在一起，更是艱難的挑戰。其中高頻電路更是深受影響，高頻訊號因距離縮短產生更強的耦合效應對電路性能的影響是不可避免的。而其中的VCO、倍頻器以及除頻器等電路，在能量的損耗以及性能的要求都相當苛刻，像是低功耗、低相位雜訊、更寬頻的工作範圍亦或是不同的特性。
因此本文分成三部分，分別為三電感耦合VCO、藉由VT調頻之低功耗三倍頻器以及tail耦合之四相位VCO。晶片使用TSMC 0.18-μm CMOS mixed-signal and RF 1P6M technology 和 TSMC 0.18-μm BICMOS mixed-signal SiGe general purpose standard process FSG Al 3P6M 1.8 & 3.3 V製作。
第一部分是由三電感互相耦合之互補式低功耗壓控震盪器，此電路是由TSMC SiGe 0.18-μm設計與模擬。首先，以互補式交錯耦合對(complementary cross-couples pair)做為壓控震盪器之主架構，再使用ADS繪製電感和萃取S參數後，將SP檔帶回VCO進行模擬並檢驗其性能。此章節將深入討論VCO的整體架構、設計理念、設計原理、模擬和量測結果。另外，主電感和兩個source degeneration電感組成的變壓器(Transformer)，不僅節省了三電感所占用的面積，同時也在功耗表現和相位雜訊上有顯著的幫助。晶片面積 0.7×0.88 mm2。
第二部分介紹了一種由VT調頻的低功耗注入鎖定三倍頻器(ILFT)，使用差動輸入基頻，經由兩顆NMOS源極串接一環型電感產生二倍諧振後，藉由NMOS混合基頻和二倍諧振，汲極產生三倍頻後，經雙圈八字電感震盪器濾除基頻和二倍諧振後輸出。在VDD為0.65，VT = 0時自振頻率為7.59 GHz，VT = 2時自振頻率為9.81 GHz。注入信號為0 dBm時，功耗為3.9 mW，注入基頻從2.4 GHz至3.4 GHz，倍三鎖定範圍為7.2 GHz至10.2 GHz。
第三部分為經tail電感耦合之QVCO，由兩組完全對稱的互補式交叉耦合對之VCO組合而成。晶片面積為1.2 × 1.1 mm2。當VDD為1.35時，功耗為2.8 mW，調頻範圍從6.29 GHz至7.09 GHz，輸出為6.32 GHz時，1 MHz之相位雜訊為-113.8866 dBc/Hz，輸出為7.09 GHz時，1 MHz之相位雜訊為-112.4584 dBc/Hz。
第四部份設計了一個9.77 GHz的LC谐振腔VCO，採用0.18μm CMOS工工藝制造。VCO核心使用單圈三葉草形狀的電感器進行噪聲抑制，同時VCO還使用两個中心抽頭耦合場效應晶體管退化源電感器來提高性能。三電感器共享一個共中空區域，以實現高效的面積设计。製造的VCO包括缓冲器在内占用的面積為1.055×0.534 mm²，可調範圍為9.77 GHz至10.82 GHz。性能指標（FOM）為-193.16 dBc/Hz.

The rapid advancement of technology has transformed our way of life, bringing unprecedented convenience and innovation. The demand for high-frequency applications has surged, presenting challenges in integrating various functions and circuits while maintaining performance in the context of shrinking process scales. High-frequency circuits, such as Voltage-Controlled Oscillators (VCOs), frequency multipliers, and dividers, face stringent requirements in terms of energy efficiency and performance, including low power consumption, low phase noise, and broader operating ranges. All designs were implemented using TSMC 0.18-μm CMOS mixed-signal and RF 1P6M technology or TSMC 0.18-μm BICMOS mixed-signal SiGe general-purpose standard process FSG Al 3P6M 1.8&3.3V.
This document is divided into three parts, each addressing specific challenges in high-frequency circuit design:
Part 1: Complementary Differential Voltage-Controlled-Oscillators with Coupled Degenerated-Source Inductors. Area and performance are two important trade-off criteria for voltage-controlled oscillator (VCO) design. This paper designs a 7.0 GHz LC-tank VCO fabricated in a 0.18 μm BiCMOS process. The VCO-core uses a two-turn 8-shaped inductor for noise suppression and the VCO also uses two center-tapped coupled FET degenerated source inductors for performance enhancement. The three inductors share a common hollow area for area-efficient design. The fabricated VCO occupies an area of 0.88×0.70 mm2 including the buffer and is tunable from 6.89 GHz to 7.49 GHz. The figure of merit (FOM) is -192.62 dBc/Hz. The VCO also exploits the explicit common-mode (CM) resonance to reduce the phase noise.
Part 2: VT-Tuned Low-Power Differential Injection-Locked Frequency Tripler. This part designs an injection-locked frequency tripler (ILFT) fabricated in a 0.18 μm CMOS process. The ILFT uses a voltage-controlled oscillator (VCO) with a two-turn 8-shaped inductor for low noise interference coupling and it also uses a frequency tripler with a common source inductor for frequency doubler generation. The two inductors are configured as a coupling factor transformer for die area saving. The fabricated ILFT with the low-coupling transformer occupies an area of 1.146×0.484 mm2 including the buffer and is tunable from 7.61 GHz to 9.81 GHz.
Part 3: Tail-Coupled Quadrature VCO (QVCO). This section designs a 6.29 GHz LC-tank quadrature voltage-controlled oscillator (QVCO) fabricated in 0.18 μm CMOS process. The fabricated QVCO occupies an area of 1.2×1.10 mm2 including the buffer and is tunable from 6.29 GHz to 7.09 GHz. The QVCO comprises two differential sub-VCOs with a two-turn 8-shaped inductor as the core resonator and the two VCOs coupled by a tail 8-shaped inductor pair as a quadruple push-push coupling device.
Part 4: This letter designs a 9.77 GHz LC-tank VCO fabricated in a 0.18μm CMOS process. The VCO-core uses a one-turn clover-shaped inductor for noise suppression and the VCO also uses two center-tapped coupled FET degenerated source inductors for performance enhancement. The three inductors share a common hollow area for area-efficient design. The fabricated VCO occupies an area of 1.055×0.534 mm2 including the buffer and is tunable from 9.77 GHz to 10.82 GHz. The figure of merit (FOM) is -193.16 dBc/Hz.

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