本論文提出具中心抽頭電感雙輸出之降壓型轉換器，一般單電感多輸出是使用傳統電感器，主要特色以中心抽頭電感延長責任週期達到更大的降壓比，並利用延長責任週期降低上臂功率級開關峰值電流改善切換損，將電感電流操作在連續導通模式，並利用相序調整方式來抑制交叉穩壓現象。
本論文採用TSMC 0.35 m 2P4M 3.3/5 V mixed-signal CMOS製程實現，晶片包含PADs之晶片面積為1.7×3.342 mm2。輸入電壓為5 V，輸出電壓分別為1.8 V及1.2 V，輸出負載範圍各為50-400 mA，外接功率級中心抽頭電感為4.7 H匝數比為1.5，輸出電容為10 F。模擬結果交叉穩壓為0.125-0.175 mV/mA，轉換器最高效率在兩輸出各100 mA為92.3%，最低效率在兩輸出各400 mA為89%。

This thesis proposes a dual-output voltage mode buck with a tapped inductor. The general single-inductor multi-output uses a traditional inductor. The main feature of this paper is to extend the duty cycle of the tapped inductor to achieve a larger step-down ratio, and to extend the responsibility. The extend cycle reduces the peak current of the upper power stage switch to improve the switching loss, operates the inductor current in continuous conduction mode, and uses phase sequence scheme to suppress the cross regulation phenomenon.
This thesis is implemented in the TMSC 0.35 m 2P4M 3.3/5 V mixed-signal CMOS process. The wafer area of the wafer containing PADs is 1.7×3.342 mm2. The input voltage is 5 V, the output voltage is 1.8 V and 1.2 V respectively, the output load range is 50-400 mA, the external power stage tapped inductance is 4.7 H, the turns ratio is 1.5, and the output capacitance is 10 F. The simulation results have a cross-regulated voltage of 0.125-0.175 mV/mA. The maximum efficiency of the converter is 92.3% for each of the two outputs of 100 mA, and the lowest efficiency is 89% for each of the two outputs of 400 mA.

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