本論文主要針對天線陣列中波束調相技術進行先期的研究。根據系統要求必須產生頻率為400 MHz的16相位時脈，為了提供天線陣列系統準確且高品質的16相位控制信號，我們提出利用鎖相迴路先將較易取得的100 MHz參考輸入信號升頻至1600 MHz，利用四相位電壓控制震盪器產生頻率為1600 MHz的正交四相位信號，再以鎖相迴路產生的正交四相位信號作為注入式鎖定除頻器的注入信號，降頻並分出頻率為400 MHz 的等相差16相位時脈，以上為本論文提出的應用於5G天線陣列波束調相之400 MHz 16相位精確時脈產生電路。
在本論文提出的系統中，我們先利用鎖相迴路作為頻率合成器將100 MHz輸入參考信號升頻至1600 MHz，其中，鎖相迴路架構包含：相位頻率偵測器、動態電流補償充電泵、四相位壓控震盪器，以及回授除法器。考量系統需求，為了要產生精準且低相位雜訊的16相位時脈，一般的環型震盪器或難以達到，因此我們提出利用LC-tank架構的四相位壓控震盪器產生準確且低相位雜訊的輸出信號，再經由注入鎖定除頻器產生16相位輸出信號。本論文提出的注入鎖定除頻器乃是利用高品質的注入信號帶動基於環型震盪器的四級差動對架構，由此產生相應的16相位信號輸出。
本論文設計晶片採用TSMC 90nm CMOS製程實現，晶片內電路全部採用Full-Custom設計流程實現。其中鎖相迴路鎖定之頻段範圍為1.525 GHz至1.7 GHz，輸入參考時脈100 MHz，系統輸出400M Hz 相差22.5˚的16相位信號。系統核心操作功率消耗約為32.69m W，晶片面積約為2.6 〖mm〗^2。

This thesis mainly focuses on the early research of beam steering technique for antenna array system. According to the system specification, we have to generate 16 signals with equal phase differences at 400 MHz. In order to provide highly accurate 16-phase control signals for the antenna array, we propose use a Phase Locked Loop (PLL) up-convert the 100 MHz reference clock to 1.6 GHz, then using a Injection Locked Frequency Divider (ILFD) to down-convert the output signals of the Quadrature- Voltage Controlled Oscillator (Q-VCO) to 400 MHz to generate 16 clocks with equal phase differences at the same time. This is the proposed “Precise 16 phases 400MHz clock generator for 5G beam steering” for this thesis.
In the proposed system, we first utilize the PLL as a frequency synthesizer to up-convert the 100 MHz reference clock to 1.6 GHz. The PLL is composed of 4 different blocks, including a Phase Frequency Detector (PFD), a Charge Pump (CP), a Quadrature- Voltage Controlled Oscillator (Q-VCO), and a frequency divider. According to the system specification, the phase difference between the 16-phase control signals has to be very precise at 22.5˚ degree. A conventional ring oscillator cannot provide signals with such highly precise phase difference. Thus, we employ an LC- tank Q-VCO to generate accurate and low phase noise output signals, then use the ILFD to generate the 16 phases output. The ILFD we used, has a 4- stage differential structure with high quality quadrature injecting signals, the ILFD can generate 16-phase output clocks.
The chip is fabricated in TSMC 90nm CMOS process technology. The frequency tuning rang of the PLL is from 1.525 GHz to 1.7 GHz. The frequency of the input reference is 100 MHz, the output 16 phases have equal phase difference of 22.5˚ at 400 MHz. The core power consumption is approximately 32.69 mW, and the chip size is approximately 2.6 〖mm〗^2.

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